SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 12-4 lists the memory-mapped registers for the ACMP. All register offset addresses not listed in Table 12-4 should be considered as reserved locations and the register contents should not be modified.
The offsets are relative to the Analog Comparator base address of 0x4003C000. Note that the analog comparator clock must be enabled before the registers can be programmed (see Section 4.2.98). There must be a delay of 3 system clock cycles after the analog comparator module clock is enabled before any analog comparator module registers are accessed.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | ACMIS | Analog Comparator Masked Interrupt Status | Section 12.5.1 |
| 0x4 | ACRIS | Analog Comparator Raw Interrupt Status | Section 12.5.2 |
| 0x8 | ACINTEN | Analog Comparator Interrupt Enable | Section 12.5.3 |
| 0x10 | ACREFCTL | Analog Comparator Reference Voltage Control | Section 12.5.4 |
| 0x20 | ACSTAT0 | Analog Comparator Status 0 | Section 12.5.5 |
| 0x24 | ACCTL0 | Analog Comparator Control 0 | Section 12.5.6 |
| 0x40 | ACSTAT1 | Analog Comparator Status 1 | Section 12.5.5 |
| 0x44 | ACCTL1 | Analog Comparator Control 1 | Section 12.5.6 |
| 0x60 | ACSTAT2 | Analog Comparator Status 2 | Section 12.5.5 |
| 0x64 | ACCTL2 | Analog Comparator Control 2 | Section 12.5.6 |
| 0xFC0 | ACMPPP | Analog Comparator Peripheral Properties | Section 12.5.7 |
Complex bit access types are encoded to fit into small table cells. Table 12-5 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |