SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
This example transfers 64 bytes from a memory buffer to the peripheral's transmit FIFO register using µDMA channel 7. The control structure for channel 7 is at offset 0x070 of the channel control table. The channel control structure for channel 7 is located at the offsets shown in Table 8-8.
| Offset | Description |
|---|---|
| Control Table Base + 0x070 | Channel 7 source end pointer |
| Control Table Base + 0x074 | Channel 7 destination end pointer |
| Control Table Base + 0x078 | Channel 7 control word |