SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
In addition to traditional single-ended sampling, the ADC module supports differential sampling of two analog input channels. To enable differential sampling, software must set the Dn bit in the ADCSSCTL0n register in a step's configuration nibble.
When a sequence step is configured for differential sampling, the input pair to sample must be configured in the ADCSSMUXn register. Differential pair 0 samples analog inputs 0 and 1; differential pair 1 samples analog inputs 2 and 3; and so on (see Table 10-5). The ADC does not support other differential pairings such as analog input 0 with analog input 3.
Differential Pair | Analog Inputs |
---|---|
0 | 0 and 1 |
1 | 2 and 3 |
2 | 4 and 5 |
3 | 6 and 7 |
4 | 8 and 9 |
5 | 10 and 11 |
6 | 12 and 13 |
7 | 14 and 15 |
8 | 16 and 17 |
9 | 18 and 19 |
10 | 20 and 21 |
11 | 22 and 23 |
The voltage sampled in differential mode is the difference between the odd and even channels:
The input differential voltage is defined as: VIND = VIN+ – VIN–, therefore:
When using differential sampling, the following definitions are relevant:
The following conditions provide optimal results in differential mode:
If VINCM is not equal to VREFCM, the differential input signal may clip at either maximum or minimum voltage, because either single ended input can never be larger than VREFP or smaller than VREFN, and it is not possible to achieve full swing. Thus any difference in common mode between the input voltage and the reference voltage limits the differential dynamic range of the ADC.
Because the maximum peak-to-peak differential signal voltage is 2 × (VREFP – VREFN), the ADC codes are interpreted as:
Figure 10-10 shows how the differential voltage, ∆V, is represented in ADC codes.