4.2.15 DIVSCLK Register (Offset = 0x148) [reset = 0x0]
Divisor and Source Clock Configuration (DIVSCLK)
The DIVSCLK register specifies the source and divisor of the DIVSCLK reference clock output. This signal can be used as a clock source to an external device but bears no timing relationship to other signals.
NOTE
The DIVSCLK signal output is not synchronized to the System Clock.
DIVSCLK is shown in Figure 4-21 and described in Table 4-27.
Return to Summary Table.
Figure 4-21 DIVSCLK Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| EN |
RESERVED |
SRC |
| R/W-0x0 |
R-0x0 |
R/W-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
DIV |
| R-0x0 |
R/W-0x0 |
|
Table 4-27 DIVSCLK Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
EN |
R/W |
0x0 |
DIVSCLK Enable.
This bit enables the generation of the DIVSCLK clock output. It resets to 0 to disable the output thereby reducing initial current/power consumption.
0x0 = The clock output is disabled.
0x1 = Clock output is enabled.
|
| 30-18 |
RESERVED |
R |
0x0 |
|
| 17-16 |
SRC |
R/W |
0x0 |
Clock Source.
Selects the reference clock used to generate the output.
0x0 = System clock
0x1 = PIOSC
0x2 = MOSC
0x3 = Reserved
|
| 15-8 |
RESERVED |
R |
0x0 |
|
| 7-0 |
DIV |
R/W |
0x0 |
Divisor Value.
This field controls the ratio of the source clock to the output clock. The output clock frequency is equal to the source clock frequency divided by the DIV field value plus 1.
0x0 = Divided by 1
0x1 = Divided by 2
|