SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The SHA/MD5 module can operate in µDMA mode where the module can assert a µDMA request for context in, context out, or data input. The µDMA signals that can be generated are:
The SHA/MD5 Module be programmed to assert an interrupt when the µDMA has completed its last transfer by programming the SHA DMA Interrupt Mask (SHA_DMAIM), at the CRC and Cryptographic Modules (CCM) offset 0x010. The SHA DMA Raw Interrupt Status (SHA_DMARIS) register, at CCM offset 0x014, indicates when the µDMA has completed and can be cleared by the SHA DMA Interrupt Clear (SHA_DMAIC) register at CCM offset 0x01C.
NOTE
The SHA module can only be accessed through privileged mode. If the µDMA is used for SHA transfers, then the µDMA's DMA Channel Control (DMACHCTL) register also needs to be programmed to allow for privileged accesses.
If context and data transfers are to be handled through software in Interrupt Mode, then the SHA Interrupt Enable (SHA_IRQENABLE), offset 0x11C, can be used to enable interrupt triggering when context out, context in, data in or data out is ready. The SHA Interrupt Status (SHA_IRQSTATUS), offset 0x118, indicates when an interrupt is triggered.
NOTE
If the application uses Interrupt Mode, an interrupt is generated for each block of processed data. To support larger data flow, SHA µDMA Mode should be used and the bits in the SHA_IRQENABLE register should be cleared.
| Event | Description |
|---|---|
| SHA_IRQSTATUS [3]: CONTEXT_OUT | Context output interrupt |
| SHA_IRQSTATUS [1]: DATA_IN | Data input interrupt |
| SHA_IRQSTATUS [0]: CONTEXT_IN | Context input interrupt |