SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
If a bus error occurs while the DMA controller is accessing memory, the DMA controller immediately terminates the DMA transfer and interrupts the processor with a bus error by setting the ERR bit in the USBDMACTLn register.
NOTE
The generation of the bus error interrupt is not affected by setting the IE bit in the USBDMACTL register. This bus error interrupt is still generated even if the IE bit is 0.