SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The integrated DMA of the Ethernet Controller is used to optimize data transfer between the MAC and system SRAM. The DMA has independent transmit and receive engines.
The DMA transmit engine transfers data from system memory to the Ethernet TX/RX Controller, while the receive engine transfers data from the RX FIFO to the system memory. The controller uses descriptors to efficiently move data from source to destination with minimal CPU intervention. The DMA is designed for packet-oriented data transfers such as frames in Ethernet. Fixed burst lengths of 1, 4, 8, or 16 words are supported with reinitiation of bursts when retry or burst termination responses occur. For a burst retry, if the remaining address count is greater than 1 and the RIB bit in the Ethernet MAC DMA Bus Mode (EMACDMABUSMOD) register is clear, then the transfer resends data in one continuous burst. When one transfer is left, it is done as a single burst and the transaction is terminated immediately afterward. If the RIB bit in the EMACDMABUSMOD register is set, the DMA sends the remaining data in fixed burst sizes of 1, 4, 8, or 16 words.
The application may also choose between solely fixed bursts or mixed bursts by the DMA. If the MB bit is set and the FB bit is clear in the EMACDMABUSMOD register, then the DMA uses fixed bursts for burst sizes less than 16 and a full, non-divided burst for lengths greater than 16. Fixed burst lengths allow for more DMA bus arbitration with other masters. Maximum burst transfer lengths can be programmed for both the receive and transmit channels of the DMA through the PBL, RPBL, and 8xPBL bit fields in the EMACDMABUSMOD register.
The DMA Controller requests a read transfer only when it can accept the received burst data completely. Data read from the bus is always pushed into the DMA without any delay or busy cycles. The DMA requests write transfers only when it has sufficient data to transfer the burst completely. When operating in fixed burst length mode, the DMA interface continues to burst with dummy data until the specified length is completed. The Ethernet controller can be programmed to interrupt the CPU in situations such as Frame Transmit and Receive transfer completion, and other normal/error conditions.
The integrated Ethernet DMA communicates through two data structures:
The DMA writes data frames received by the MAC to the receive buffer in system memory and transfers data frames for transmission from system memory to the MAC. Descriptors that reside in the system memory act as pointers to these buffers.
There are two descriptor lists: one for reception and one for transmission. The base address of each list is written into the Ethernet MAC Receive Descriptor List Address (EMACRXDLADDR) register at offset 0xC0C and the Ethernet Mac Transmit Descriptor List Address (EMACTXDLADDR) register at offset 0xC10, respectively.
The descriptor structure can contain up to 8 words (32 bytes). These are described in more detail in Section 15.3.3.5. A descriptor list is forward linked (either implicitly or explicitly). The last descriptor may point back to the first entry to create a ring structure. Explicit chaining of descriptors is accomplished by enabling second address chaining in both the Receive and Transmit descriptors (RDES0[14] and TDES0[20]). The descriptor lists reside in the SRAM address space. Each descriptor can point to a maximum of two buffers. This enables two buffers to be used at different physical addresses rather than contiguous buffers in memory.
The data buffer also resides in the physical memory space and consists of an entire frame or part of a frame, but cannot exceed a single frame. Buffers contain only data and buffer status is maintained in the descriptor. Data chaining refers to frames that span multiple data buffers. However, a single descriptor cannot span multiple frames. The DMA skips to the next frame buffer when the end-of-frame is detected. Data chaining can be enabled or disabled through the descriptors.
NOTE
The EMAC DMA Controller only has access to internal system SRAM.