SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The QSSI peripheral provides an interface to the µDMA controller with separate channels for transmit and receive. The µDMA operation of the QSSI is enabled through the SSI DMA Control (SSIDMACTL) register. When µDMA operation is enabled, the QSSI asserts a µDMA request on the receive or transmit channel when the associated FIFO can transfer data.
For the receive channel, a single transfer request is asserted whenever any data is in the receive FIFO. A burst transfer request is asserted whenever the amount of data in the receive FIFO is 4 or more items. For the transmit channel, a single transfer request is asserted whenever at least one empty location is in the transmit FIFO. The burst request is asserted whenever the transmit FIFO has 4 or more empty slots. The single and burst µDMA transfer requests are handled automatically by the µDMA controller depending how the µDMA channel is configured.
To enable µDMA operation for the receive channel, the RXDMAE bit of the DMA Control (SSIDMACTL) register should be set after configuring the µDMA. To enable µDMA operation for the transmit channel, the TXDMAE bit of SSIDMACTL should be set after configuring the µDMA.
If the µDMA is enabled and has completed a data transfer from the Tx FIFO, the DMATXRIS bit is set in the SSIRIS register and cannot be cleared by setting the DMATXIC bit in the SSI Interrupt Clear (SSIICR) register. In the DMA Completion Interrupt Service Routine, software must disable the µDMA transmit enable to the SSI by clearing the TXDMAE bit in the QSSI DMA Control (SSIDMACTL) register and then setting the DMATXIC bit in the SSIICR register. This clears the DMA completion interrupt. When the µDMA is needed to transmit more data, the TXDMAE bit must be set (enabled) again.
If a data transfer by the µDMA from the Rx FIFO completes, the DMARXRIS bit is set. The EOT bit in the SSIRIS register is also provided to indicate when the Tx FIFO is empty and the last bit has been transmitted out of the serializer
NOTE
Wait states are inserted at every byte transfer when using Bi- or Quad-SSI modes as a master with the µDMA at SSICLK frequencies greater than one sixth of the system clock. These wait states are because of arbitration stall cycles from the µDMA accesses to SRAM and increased output throughput from the SSI.
See Section 8 for more details about programming the µDMA controller.