4.2.14 DSCLKCFG Register (Offset = 0x144) [reset = 0x0]
Deep Sleep Clock Configuration Register (DSCLKCFG)
The DSCLKCFG register specifies the behavior of the clock system while in deep sleep.
The MOSCDPD bit affects not only deep-sleep mode, but all other modes as well depending on the value of the bit. See Table 4-25 when programming this bit:
Table 4-25 MOSC Configurations
| PWRDN Bit |
MOSCDPD Field |
Result |
| 0 |
0 |
MOSC is powered on in run and sleep modes, but is disabled in accidental power down, when the PWRDN bit is set in the MOSCCTL register, or in deep-sleep mode only if it is not the deep-sleep clock source (DSOSCSRC !== 0x3). |
| 0 |
1 |
MOSC is powered and running in run, sleep, and deep-sleep modes. |
| 1 |
0 |
MOSC is powered off and does not run in any mode. In this configuration, when the MOSC is disabled, choosing the MOSC as a clock source causes in indeterminate results. |
| 1 |
1 |
MOSC runs and does not disable itself in run, sleep, and deep-sleep modes regardless of the whether or not the PWRDN bit is set. |
NOTE
The MOSCDPD bit has an effect in all modes of operation
NOTE
If the MOSC is chosen as the deep-sleep clock source in the DSCLKCFG register, the MOSC must also be configured as the run and sleep clock source in the RSCLKCFG register before entering deep sleep. If the PIOSC, LFIOSC, or Hibernation RTC module oscillator (HIBLFIOSC or 32-kHz crystal) is configured as the run and sleep clock source in the RSCLKFCFG register, and the MOSC is configured as the deep-sleep clock source in the DSCLKCFG register, then two outcomes are possible:
- If the PIOSC is still powered in deep sleep (using the PIOSCPD bit in the DSCLKCFG register) then the PIOSC is used as the clock source when entering deep sleep and the device enters and exits the deep-sleep mode normally. The MOSC is not used as the clock source in deep sleep.
- If the PIOSC has been configured to be powered down in deep sleep, then the device can enter the deep-sleep mode, but cannot exit properly. This situation can be avoided by programming the MOSC as the run and sleep clock source in the RSCLKCFG register before entering deep sleep.
DSCLKCFG is shown in Figure 4-20 and described in Table 4-26.
Return to Summary Table.
Figure 4-20 DSCLKCFG Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| PIOSCPD |
MOSCDPD |
RESERVED |
| R/W-0x0 |
R/W-0x0 |
R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| DSOSCSRC |
RESERVED |
| R/W-0x0 |
R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
DSSYSDIV |
| R-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| DSSYSDIV |
| R/W-0x0 |
|
Table 4-26 DSCLKCFG Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31 |
PIOSCPD |
R/W |
0x0 |
PIOSC Power Down
0x0 = The PIOSC is active during deep-sleep mode.
0x1 = The PIOSC is disabled during sleep mode for additional power savings.
|
| 30 |
MOSCDPD |
R/W |
0x0 |
MOSC Disable Power Down.
This bit inhibits the MOSC from automatic or accidental power down. This bit is defined to ensure the MOSC circuit cannot be interrupted in uses where MOSC supplies a clock to the peripherals (for example, Ethernet PHY).
0x0 = During deep-sleep (if DSOSCSRC is not MOSC), accidental power down or when the PWRDWN bit is set in the MOSCCTL register, the MOSC is powered down.
0x1 = MOSC is not powered off during automatic or accidental power down. MOSC is also not powered off if DSOSCRC is programmed to be MOSC.
This bit should be set only after software configures the MOSCCTL register. Setting the MOSCDPD bit masks writes to PWRDN bit in the MOSCCTL register.
|
| 29-24 |
RESERVED |
R |
0x0 |
|
| 23-20 |
DSOSCSRC |
R/W |
0x0 |
Deep Sleep Oscillator Source.
This field specifies the oscillator source that becomes the oscillator clock (OSCCLK) source, which is used when the PLL is bypassed during deep-sleep mode.
0x0 = Reserved
0x1 = Reserved
0x2 = LFIOSC
0x3 = MOSC
0x4 = Hibernation module RTCOSC
|
| 19-10 |
RESERVED |
R |
0x0 |
|
| 9-0 |
DSSYSDIV |
R/W |
0x0 |
Deep Sleep Clock Divisor.
This field specifies the system clock divisor value during deep-sleep mode. The clock source selected by DSOSCSRC is divided by DSSYSDIV + 1:
fSYSCLK = fOSCCLK / (DSSYSDIV + 1)
Values 0x0 and 0x1 should not be used.
If deep-sleep clock divide by 1 or divide by 2 is desired, the OSYSDIV bit field of the RSCLKCFG register must be configured for the desired deep-sleep divider before entering deep sleep. In this case, the Q post-divider bit field in the PLLFREQ1 register may need to be adjusted to keep the system clock frequency within the maximum clock frequency before entering deep sleep. |