31-17 |
RESERVED |
R |
0x0 |
|
16 |
NIE |
R/W |
0x0 |
Normal Interrupt Summary Enable. This bit enables/masks the ERI, RI, TU, and TI bits in MAC DMA Interrupt Status Register (EMACDMARIS)
0x0 = Normal interrupt summary is masked.
0x1 = Normal interrupt summary is enabled.
|
15 |
AIE |
R/W |
0x0 |
Abnormal Interrupt Summary Enable. This bit enables/masks the TPS, TJT, OVF, UNF, RU, RPS, RWT, ETI and FBI bits in MAC DMA Interrupt Status Register (EMACDMARIS)
0x0 = Abnormal interrupt summary is disabled.
0x1 = Abnormal interrupt summary is enabled.
|
14 |
ERE |
R/W |
0x0 |
Early Receive Interrupt Enable.
0x0 = Early receive interrupt is disabled.
0x1 = Early receive interrupt is enabled. Normal Interrupt Summary Enable (NIE, bit 16) must also be set to 0x1.
|
13 |
FBE |
R/W |
0x0 |
Fatal Bus Error Enable.
0x0 = Fatal Bus Error Enable Interrupt is disabled.
0x1 = Fatal Bus Error Interrupt is enabled. Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
|
12-11 |
RESERVED |
R |
0x0 |
|
10 |
ETE |
R/W |
0x0 |
Early Transmit Interrupt Enable.
0x0 = Early Transmit Interrupt is disabled.
0x1 = Early Transmit Interrupt is enabled. Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
|
9 |
RWE |
R/W |
0x0 |
Receive Watchdog Time-out Enable.
0x0 = The Receive Watchdog Time-out Interrupt is disabled.
0x1 = The Receive Watchdog Time-out Interrupt is enabled. Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
|
8 |
RSE |
R/W |
0x0 |
Receive Stopped Enable.
0x0 = Receive Stopped Interrupt is disabled.
0x1 = Receive Stopped Interrupt is enabled. Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
|
7 |
RUE |
R/W |
0x0 |
Receive Buffer Unavailable Enable.
0x0 = The Receive Buffer Unavailable Interrupt is disabled.
0x1 = The Receive Buffer Unavailable Interrupt is enabled. Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
|
6 |
RIE |
R/W |
0x0 |
Receive Interrupt Enable.
0x0 = The Receive Interrupt is disabled.
0x1 = The Receive Interrupt is enabled. Normal Interrupt Summary Enable (NIE, bit 15) must also be set to 0x1.
|
5 |
UNE |
R/W |
0x0 |
Underflow Interrupt Enable.
0x0 = Transmit Underflow Interrupt is disabled.
0x1 = The Transmit Underflow Interrupt is enabled Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
|
4 |
OVE |
R/W |
0x0 |
Overflow Interrupt Enable.
0x0 = The Overflow Interrupt is disabled.
0x1 = The Receive Overflow Interrupt is enabled. Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
|
3 |
TJE |
R/W |
0x0 |
Transmit Jabber Time-out Enable.
0x0 = Transmit Jabber Time-out Interrupt is disabled.
0x1 = Transmit Jabber Time-out Interrupt is enabled. Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
|
2 |
TUE |
R/W |
0x0 |
Transmit Buffer Unvailable Enable.
0x0 = Transmit Buffer Unavailable Interrupt is disabled.
0x1 = Transmit Buffer Unavailable Interrupt is enabled. Normal Interrupt Summary Enable (NIE, bit 15) must also be set to 0x1.
|
1 |
TSE |
R/W |
0x0 |
Transmit Stopped Enable.
0x0 = Transmission Stopped Interrupt is disabled.
0x1 = Transmission Stopped Interrupt is enabled. Abnormal Interrupt Summary Enable (AIE, bit 15) must also be set to 0x1.
|
0 |
TIE |
R/W |
0x0 |
Transmit Interrupt Enable.
0x0 = Transmit Interrupt is disabled.
0x1 = Transmit Interrupt is enabled. Normal Interrupt Summary Enable (NIE, bit 15) must also be set to 0x1.
|