| 31-27 |
RESERVED |
R |
0x0 |
|
| 26 |
DT |
R/W |
0x0 |
Disable Dropping of TCP/IP Checksum Error Frames.
0x0 = All error frames are dropped if the FEF bit is reset.
0x1 = The MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload.
|
| 25 |
RSF |
R/W |
0x0 |
Receive Store and Forward.
0x0 = The RX FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits.
0x1 = The TX/RX Controller reads a frame from the RX FIFO only after the complete frame has been written to it, ignoring the RTC bits.
|
| 24 |
DFF |
R/W |
0x0 |
Disable Flushing of Received Frames.
0x0 = RX DMA flushes frames based on receive descriptors or buffers.
0x1 = The RX DMA does not flush any frames because of the unavailability of receive descriptors or buffers.
|
| 23-22 |
RESERVED |
R |
0x0 |
|
| 21 |
TSF |
R/W |
0x0 |
Transmit Store and Forward.
0x0 = Transmission starts according to TTC bit field.
0x1 = Transmission starts when a full frame resides in the TX/RX Controller Transmit FIFO. Additionally, the TTC values specified in TTC bits[16:14] are ignored. This bit should be changed only when the transmission is stopped.
|
| 20 |
FTF |
R/W |
0x0 |
Flush Transmit FIFO. This bit is cleared internally when the flushing operation is completed. This register should not be written to until the FTF bit is cleared. The data which has already been accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. The flush operation is complete only when the TX FIFO is emptied of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host.
0x0 = This bit indicated normal operation or that the flushing operation has completed.
0x1 = The transmit FIFO controller logic is reset to its default values and thus all data in the TX FIFO is lost or flushed.This bit is cleared internally when the flushing operation is complete.
|
| 19-17 |
RESERVED |
R |
0x0 |
|
| 16-14 |
TTC |
R/W |
0x0 |
Transmit Threshold Control. These bits control the threshold level of the TX/RX Controller Transmit FIFO. Transmission starts when the frame size within the TX/RX Controller Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset.
0x0 = 64 bytes
0x1 = 128 bytes
0x2 = 192 bytes
0x3 = 256 bytes
0x4 = 40 bytes
0x5 = 32 bytes
0x6 = 24 bytes
0x7 = 16 bytes
|
| 13 |
ST |
R/W |
0x0 |
Start or Stop Transmission Command.
When this bit is set, transmission is placed in the running state. The DMA attempts to acquire the descriptor from the Transmit Descriptor List. Descriptor acquisition is attempted from the current position in the list, which is the Transmit List Base Address set by Transmit Descriptor List Address (EMACTXDLADDR) register, or from the position retained when transmission was stopped previously.
If the DMA does not own the current descriptor, transmission enters the suspended state and bit[2] (Transmit Buffer Unavailable, TU) of the MAC DMA Raw Interrupt Status Register (EMACDMARIS) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting EMACTXDLADDR, then the DMA behavior is unpredictable.
When this bit is cleared, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program EMACTXDLADDR with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state.
0x0 = Transmission process is placed in the stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted.
0x1 = Transmission is placed in the running state, and the DMA checks the transmit list at the current position for a frame to be transmitted.
|
| 12-8 |
RESERVED |
R |
0x0 |
|
| 7 |
FEF |
R/W |
0x0 |
Forward Error Frames. When this bit is reset, the RX FIFO drops frames with error status (CRC error, collision error, MII_ER, giant frame, watchdog time-out, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the RX controller side (in Threshold mode), then the frame is not dropped. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If Bit 25, Receive Store and Forward (RSF), is set and the RX FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the RSF is reset and the RX FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA.
0x0 = The Receive FIFO drops frames with error status
0x1 = All frames except runt error frames are forwarded to the DMA.
|
| 6 |
FUF |
R/W |
0x0 |
Forward Undersized Good Frames.
0x0 = The Receive FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold (RTC) bit field (for example, RTC = 0x1).
0x1 = The Receive FIFO forwards undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC.
|
| 5 |
DGF |
R/W |
0x0 |
Drop Giant Frame Enable.
0x0 = The MAC does not drop the giant frames in the RX FIFO.
0x1 = The MAC drops received frames larger than the computed giant frame limit in the RX FIFO.
|
| 4-3 |
RTC |
R/W |
0x0 |
Receive Threshold Control. These two bits control the threshold level of the RX FIFO. Transfer (request) to DMA starts when the frame size within the RX FIFO is larger than the threshold. In addition, full frames with length less than the threshold are transferred automatically. These bits are valid only when the RSF bit (bit 25) of the EMACDMAOPMODE is zero, and are ignored when the RSF bit is set to 1.
0x0 = 64 bytes
0x1 = 32 bytes
0x2 = 96 bytes
0x3 = 128 bytes
|
| 2 |
OSF |
R/W |
0x0 |
Operate on Second Frame.
0x0 = DMA processes frames normally.
0x1 = DMA processes second frame of the Transmit data even before the status for the first frame is obtained.
|
| 1 |
SR |
R/W |
0x0 |
Start or Stop Receive.
When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by the Receive Descriptor List Address Register (EMACRXDLADDR) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable, RU) of the MAC DMA Interrupt Status Register (EMACDMARIS) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting EMACRXDLADDR, the DMA behavior is unpredictable.
When this bit is cleared, the receive DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state.
0x0 = The receive DMA operation is stopped after the transfer of the current frame
0x1 = The Receive process is placed in the Running state.
|
| 0 |
RESERVED |
R |
0x0 |
|