SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
LPI Timers Control (EMACLPITIMERCTRL)
This register controls the time-out values in the LPI modes. It specifies the time that the MAC transmits the LPI pattern and also the time that the MAC waits before resuming the normal transmission.
EMACRIS is shown in Figure 15-29 and described in Table 15-38.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | LST | ||||||||||||||
| R-0x0 | R/W-0x3E8 | ||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TWT | |||||||||||||||
| R/W-0x0 | |||||||||||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-26 | RESERVED | R | 0x0 |
|
| 25-16 | LST | R/W | 0x3E8 | LPI LS Timer.
Specifies the minimum time (in milliseconds) that the link status from the PHY should be up (OKAY) before the LPI pattern is transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LST reaches the programmed terminal count. The default value of this bit is 1000 (1 second) as defined in the IEEE standard. |
| 15-0 | TWT | R/W | 0x0 | LPI TW Timer.
Specifies the minimum time (in microseconds) that the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after this timer expires. |