15.6.26 EMACMMCRXRIS Register (Offset = 0x104) [reset = 0x0]
Ethernet MAC MMC Receive Raw Interrupt Status (EMACMMCRXRIS)
The MAC MMC Receive Interrupt (EMACMMCRXRIS) register maintains the interrupts that are generated when the following happens:
- Receive statistic counters reach half of their maximum values (0x80000000 for 32-bit counter and 0x8000 for 16-bit counter).
- Receive statistic counters cross their maximum values (0xFFFFFFFF for 32-bit counter and 0xFFFF for 16-bit counter).
When the Counter Stop Rollover (CNTSTPRO bit) in the MAC MMC Control (EMACMMCCTRL) register is set, interrupts are set but the counter remains at all-ones. The EMACMMCRXRIS register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
EMACMMCRXRIS is shown in Figure 15-41 and described in Table 15-50.
Return to Summary Table.
Figure 15-41 EMACMMCRXRIS Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
UCGF |
RESERVED |
| R-0x0 |
R-0x0 |
R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
ALGNERR |
CRCERR |
RESERVED |
GBF |
| R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
R-0x0 |
|
Table 15-50 EMACMMCRXRIS Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-18 |
RESERVED |
R |
0x0 |
|
| 17 |
UCGF |
R |
0x0 |
MMC Receive Unicast Good Frame Counter Interrupt Status.
0x0 = The receive Ethernet MAC Receive Frame Count for Good Unicast Frames (EMACRXCNTGUNI) register has not reached half of the maximum value or the maximum value.
0x1 = The receive Ethernet MAC Receive Frame Count for Good Unicast Frames (EMACRXCNTGUNI) register has reached half of the maximum value or the maximum value.
|
| 16-7 |
RESERVED |
R |
0x0 |
|
| 6 |
ALGNERR |
R |
0x0 |
MMC Receive Alignment Error Frame Counter Interrupt Status.
0x0 = The Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR) register has not reached half of the maximum value or the maximum value.
0x1 = The Ethernet MAC Receive Frame Count for Alignment Error Frames (EMACRXCNTALGNERR) register has reached half of the maximum value or the maximum value.
|
| 5 |
CRCERR |
R |
0x0 |
MMC Receive CRC Error Frame Counter Interrupt Status.
0x0 = The Ethernet MAC Receive Frame Count for CRC Error Frames (EMACRXCNTCRCERR) register has not reached half of the maximum value or the maximum value.
0x1 = The Ethernet MAC Receive Frame Count for CRC Error Frames (EMACRXCNTCRCERR) register has reached half of the maximum value or the maximum value.
|
| 4-1 |
RESERVED |
R |
0x0 |
|
| 0 |
GBF |
R |
0x0 |
MMC Receive Good Bad Frame Counter Interrupt Status.
0x0 = The Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB) register has not reached half of the maximum value or the maximum value.
0x1 = The Ethernet MAC Receive Frame Count for Good and Bad Frames (EMACRXCNTGB) register has reached half of the maximum value or the maximum value.
|