SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Ethernet MAC PPS Control (EMACPPSCTRL)
This register is used to control the EN0PPS signal output.
NOTE
The PTP reference clock referred to below is MOSC clock in course update mode and in fine correction mode, is the clock tick at which the system time gets updated.
EMACPPSCTRL is shown in Figure 15-66 and described in Table 15-75.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | |||||||
| R-0x0 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | TRGMODS0 | PPSEN0 | PPSCTRL | ||||
| R-0x0 | R-0x0 | R-0x0 | R/W-0x0 | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-7 | RESERVED | R | 0x0 |
|
| 6-5 | TRGMODS0 | R | 0x0 |
Target Time Register Mode for PPS0 Output. This field indicates the Target Time registers (EMACTARGSEC and EMACTARGNANO) mode for the EN0PPS output signal: 0x0 = Indicates that the Target Time registers are programmed only for generating the interrupt event. 0x1 = Reserved 0x2 = Indicates that the Target Time registers are programmed for generating the interrupt event and starting or stopping the generation of the EN0PPS output signal. 0x3 = Indicates that the Target Time registers are programmed only for starting or stopping the generation of the EN0PPS output signal. No interrupt is asserted. |
| 4 | PPSEN0 | R | 0x0 |
Flexible PPS Output Mode Enable. 0x0 = Bits[3:0] function as PPS output frequency control (PPSCTRL). 0x1 = Bits[3:0] function as PPS Command (PPSCMD). |
| 3-0 | PPSCTRL | R/W | 0x0 |
EN0PPS Output Frequency Control (PPSCTRL) or Command Control (PPSCMD). This bit field has two different functions depending on how the PPSEN0 bit is set. See the values in Table 15-76. If the PPSEN0 bit is set to 0x0, this field functions as a PPS0 output frequency control (PPSCTRL), which controls the frequency of the output signal, EN0PPS. The default value of this field is 0x0 and the PPS output is one pulse every second. If the PPSEN0 bit is 0x1, this field functions as a flexible output command control for the EN0PPS signal. Programming the PPSCTRL bit field with a non-zero value instructs the MAC to initiate an event. When the command is transferred or synchronized to the PTP clock domain, these bits are cleared automatically. Software should ensure that these bits are programmed only when they are "all-zeros." In the binary rollover mode, the EN0PPS signal has a duty cycle of 50 percent with these frequencies. In the digital rollover mode, the EN0PPS signal frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example: When PPSCTRL = 0x1, EN0PPS (1 Hz) has a low period of 537 ms and a high period of 463 ms. When PPSCTRL = 0x2, EN0PPS (2 Hz) is a sequence of: - One clock of 50 percent duty cycle and 537 ms period - Second clock of 463 ms period (268 ms low and 195 ms high) When PPSCTRL = 0x3, EN0PPS (4 Hz) is a sequence of: - Three clocks of 50 percent duty cycle and 268 ms period - Fourth clock of 195 ms period (134 ms low and 61 ms high) This signaling behavior is because of the non-linear toggling of bits in the digital rollover mode in the Ethernet MAC System Time - Nanoseconds (EMACTIMNANO) register. |
| Value | Description |
|---|---|
| 0x0 |
When the PPSEN0 bit = 0x0, the EN0PPS signal is 1 pulse of the PTP reference clock. every second. When the PPSEN0 bit = 0x1, this encoding indicates no command. |
| 0x1 |
When the PPSEN0 bit = 0x0, the binary rollover is 2 Hz, and the digital rollover is 1 Hz. When the PPSEN0 bit = 0x1, START single pulse. This command generates a single pulse rising at the start point defined in the Ethernet MAC Target Time Second/Nanoseconds (EMACTARGX) registers (MAC offsets 0x71C and 0x720) and a duration defined in the Ethernet MAC PPS0 Width (EMACPPS0WIDTH) register (offset 0x764). |
| 0x2 |
When the PPSEN0 bit = 0x0, the binary rollover is 4 Hz, and the digital rollover is 2 Hz. When the PPSEN0 bit = 0x1, START pulse train. This command generates the train of pulses rising at the start point defined in the Ethernet MAC Target Time Second/Nanoseconds (EMACTARGX) registers (MAC offsets 0x71C and 0x720) and repeated at an interval defined in the Ethernet MAC PPS0 Width (EMACPPS0WIDTH) register (offset 0x764). By default, the EN0PPS pulse train is free-running unless stopped by STOP pulse train at a time or STOP pulse train immediately command. |
| 0x3 |
When the PPSEN0 bit = 0x0, the binary rollover is 8 Hz, and the digital rollover is 4 Hz, When the PPSEN0 bit = 0x1, cancel START. This command cancels the START single pulse and START pulse train commands if the system time has not crossed the programmed start time. |
| 0x4 |
When the PPSEN0 bit = 0x0, the binary rollover is 16 Hz, and the digital rollover is 8 Hz. When the PPSEN0 bit = 0x1, STOP pulse train at time. This command stops the train of puses initiated by the START pulse train command after the time programmed in the Ethernet MAC Target Time Second/Nanoseconds (EMACTARGX) registers (MAC offsets 0x71C and 0x720). |
| 0x5 |
When the PPSEN0 bit = 0x0, the binary rollover is 32 Hz, and the digital rollover is 16 Hz. When the PPSEN0 bit = 0x1, STOP pulse train immediately. This command immediately stops the train of pulses initiated by the START pulse train command. |
| 0x6 |
When the PPSEN0 bit = 0x0, the binary rollover is 64 Hz, and the digital rollover is 32 Hz. When the PPSEN0 bit = 0x1, cancel STOP pulse train. This command cancels the STOP pulse train at the time command if the programmed stop time has not elapsed. The EN0PPS pulse train becomes free-running on the successful execution of this command. |
| 0x7 |
When the PPSEN0 bit = 0x0, the binary rollover is 128 Hz, and the digital rollover is 64 Hz. When the PPSEN0 bit = 0x1, this encoding is reserved. |
| 0x8 |
When the PPSEN0 bit = 0x0, the binary rollover is 256 Hz, and the digital rollover is 128 Hz. When the PPSEN0 bit = 0x1, this encoding is reserved. |
| 0x9 |
When the PPSEN0 bit = 0x0, the binary rollover is 512 Hz, and the digital rollover is 256 Hz. When the PPSEN0 bit = 0x1, this encoding is reserved. |
| 0xA |
When the PPSEN0 bit = 0x0, the binary rollover is 1.024 kHz, and the digital rollover is 512 Hz. When the PPSEN0 bit = 0x1, this encoding is reserved. |
| 0xB |
When the PPSEN0 bit = 0x0, the binary rollover is 2.048 kHz, and the digital rollover is 1.024 kHz. When the PPSEN0 bit = 0x1, this encoding is reserved. |
| 0xC |
When the PPSEN0 bit = 0x0, the binary rollover is 4.096 kHz, and the digital rollover is 2.048 kHz. When the PPSEN0 bit = 0x1, this encoding is reserved. |
| 0xD |
When the PPSEN0 bit = 0x0, the binary rollover is 8.192 kHz, and the digital rollover is 4.096 kHz. When the PPSEN0 bit = 0x1, this encoding is reserved. |
| 0xE |
When the PPSEN0 bit = 0x0, the binary rollover is 16.384 kHz, and the digital rollover is 8.092 kHz. When the PPSEN0 bit = 0x1, this encoding is reserved. |
| 0xF |
When the PPSEN0 bit = 0x0, the binary rollover is 32.768 kHz, and the digital rollover is 16.384 kHz. When the PPSEN0 bit = 0x1, this encoding is reserved. |