SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Ethernet MAC Receive Interrupt Watchdog Timer (EMACRXINTWDT)
This register, when written with non-zero value, enables the watchdog timer for the Receive Interrupt, RI (Bit 6), of the EMACDMARIS register at EMAC offset 0xC14.
EMACRXINTWDT is shown in Figure 15-78 and described in Table 15-88.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | RIWT | ||||||||||||||||||||||||||||||
R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||