15.6.47 EMACTARGSEC Register (Offset = 0x71C) [reset = 0x0]
Ethernet MAC Target Time Seconds (EMACTARGSEC)
The MAC Target Time Seconds (EMACTARGSEC) register, along with the MAC Target Time Nanoseconds (EMACTARGNANO) register, is used to schedule an interrupt event.
EMACTARGSEC is shown in Figure 15-62 and described in Table 15-71.
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Figure 15-62 EMACTARGSEC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| TSTR |
| R/W-0x0 |
|
Table 15-71 EMACTARGSEC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-0 |
TSTR |
R/W |
0x0 |
Target Time Seconds Register. This register stores the time in seconds. When the timestamp value matches or exceeds both the MAC Target Time Seconds (EMACTARGSEC) and MAC Target Time Nanoseconds (EMACTARGNANO) registers, then based on the TRGMODS0 bit field in the MAC PPS Control (EMACPPSCTRL), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled).
|