| 31-19 |
RESERVED |
R |
0x0 |
|
| 18 |
PTPFLTR |
R/W |
0x0 |
Enable MAC address for PTP Frame Filtering.
0x0 = No effect.
0x1 = The Destination Address (DA) MAC address, that matches any MAC Address register is used to filter PTP frames when PTP is directly sent over Ethernet.
|
| 17-16 |
SELPTP |
R/W |
0x0 |
Select PTP packets for Taking Snapshots. These bits along with Bits 15 and 14 decide the set of PTP packet types for which a snapshot needs to be taken.
|
| 15 |
TSMAST |
R/W |
0x0 |
Enable Snapshot for Messages Relevant to Master.
0x0 = The snapshot is taken for the messages relevant to the slave node.
0x1 = The snapshot is taken only for the messages relevant to the master node.
|
| 14 |
TSEVNT |
R/W |
0x0 |
Enable Timestamp Snapshot for Event Messages.
0x0 = The snapshot is taken for all messages except Announce, Management, and Signaling.
0x1 = The timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
|
| 13 |
PTPIPV4 |
R/W |
0x1 |
Enable Processing of PTP Frames Sent over IPv4-UDP.
0x0 = The MAC ignores PTP transported over UDP-IPv4 packets. This bit is set by default.
0x1 = The MAC receiver processes PTP packets encapsulated in UDP over IPv4 packets.
|
| 12 |
PTPIPV6 |
R/W |
0x0 |
Enable Processing of PTP Frames Sent Over IPv6-UDP.
0x0 = The MAC ignores PTP transported over UDP-IPv6 packets.
0x1 = The MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets.
|
| 11 |
PTPETH |
R/W |
0x0 |
Enable Processing of PTP Over Ethernet Frames.
0x0 = The MAC ignores PTP over Ethernet packets.
0x1 = The MAC receiver processes PTP packets encapsulated directly in Ethernet frames.
|
| 10 |
PTPVER2 |
R/W |
0x0 |
Enable PTP Packet Processing For Version 2 Format.
0x0 = PTP packets are processed using the IEEE 1588 version 1 format.
0x1 = PTP packets are processed using the IEEE 1588 version 2 format.
|
| 9 |
DGTLBIN |
R/W |
0x0 |
Timestamp Digital or Binary Rollover Control.
0x0 = The TTSLO field of the EMACTARGNANO register, rolls over after 0x7FFF_FFFF and increments the EMACTARGSEC register. The sub-second increment has to be programmed correctly depending on the MOSC frequency and the value of this bit.
0x1 = The EMACTARGNANO register rolls over after 0x3B9A.C9FF value (that is, 1 nanosecond accuracy) and increments the EMACTARGSEC register.
|
| 8 |
ALLF |
R/W |
0x0 |
Enable Timestamp For All Frames.
0x0 = No effect.
0x1 = Timestamp snapshots are enabled for all frames received by the MAC.
|
| 7-6 |
RESERVED |
R |
0x0 |
|
| 5 |
ADDREGUP |
R/W |
0x0 |
Addend Register Update.
0x0 = No effect.
0x1 = When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it.
|
| 4 |
INTTRIG |
R/W |
0x0 |
Timestamp Interrupt Trigger Enable.
0x0 = No effect.
0x1 = The timestamp interrupt is generated when the System Time becomes greater than the value written in the Ethernet MAC Target Time Seconds/Nanoseconds (EMACTARGSEC/EMACTARGNANO) registers. This bit is reset after the generation of the Timestamp Trigger Interrupt.
|
| 3 |
TSUPDT |
R/W |
0x0 |
Timestamp Update. This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The Timestamp Higher Word register is not updated.
0x0 = No effect.
0x1 = When set, the system time is updated (added or subtracted) with the value specified in EMACTIMSECU (System Time - Seconds Update Register) and EMACTIMNANOU (System Time - Nanoseconds Update Register).
|
| 2 |
TSINIT |
R/W |
0x0 |
Timestamp Initialize. This bit should read zero before updating it.
0x0 = This bit is reset when the initialization is complete.
0x1 = The system time is initialized (overwritten) with the value specified in the Ethernet MAC System Time-Seconds Update (EMACTIMSECU) and the Ethernet MAC System Time-Nanoseconds Update (EMACTIMNANOU) registers.
|
| 1 |
TSFCUPDT |
R/W |
0x0 |
Timestamp Fine or Coarse Update.
0x0 = Indicates the system timestamp update should be done using the coarse method.
0x1 = Indicates that the system times update should be done using the fine update method.
|
| 0 |
TSEN |
R/W |
0x0 |
Timestamp Enable. The EMACTIMSEC and the EMACTIMNANO registers must be initialized after enabling this mode. On the receive side, the MAC processes 1588 frames only if this bit is set.
0x0 = The timestamp is not added for the transmit and receive frames and the timestamp generator module is also suspended.
0x1 = The timestamp is added for the transmit and receive frames
|