SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The following endian configuration is provided by the ENDIAN field in the CRCCTRL register:
Input data width is four bytes, hence the configuration only affects the four-byte word. Table 13-1 lists the configurations that the ENDIAN bit field supports, assuming the input word is {B3, B2, B1, B0}.
| ENDIAN Encoding | Definition | Configuration |
|---|---|---|
| 0x0 | Configuration unchanged. | {B3, B2, B1, B0} |
| 0x1 | Bytes are swapped in half-words but half-words are not swapped. | {B2, B3, B0, B1} |
| 0x2 | Half-words are swapped but bytes are not swapped in half-word. | {B1, B0, B3, B2} |
| 0x3 | Bytes are swapped in half-words and half-words are swapped. | {B0, B1, B2, B3} |
Bit reversal is supported by the BR bit in the CRCCTRL register. The bit reversal operation works in tandem with endian control. For example, the above table with the BR option set would look like this:
| ENDIAN Encoding | Initial Endian Configuration | Configuration With Bit Reversal (BR = 1) |
|---|---|---|
| 0x0 | Configuration unchanged.
{B3[31:24], B2[23:16], B1[15:8], B0[7:0]} |
B3[24:31],B2[16:23],B1[8:15],B0[0:7] |
| 0x1 | Bytes are swapped in half-words but half-words are not swapped.
{B2[23:16], B3[31:24], B0[7:0], B1[15:8]} |
B2[16:23],B3[24:31],B0[0:7],B1[8:15] |
| 0x2 | Half-words are swapped but bytes are not swapped in half-word.
{B1[15:8], B0[7:0], B3[31:24], B2[23:16]} |
B1[8:15],B0[0:7],B3[24:31],B2[16:23] |
| 0x3 | Bytes are swapped in half-words and half-words are swapped.
{B0[7:0], B1[15:8], B2[23:16], B3[31:24]} |
B0[0:7],B1[8:15],B2[16:23],B3[24:31] |