SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
EPI Main Baud Rate (EPIBAUD2)
The system clock is used internally to the EPI Controller. The baud rate counter can be used to divide the system clock down to control the speed on the external interface. If the mode selected emits an external EPI clock, this register defines the EPI clock emitted. If the mode selected does not use an EPI clock, this register controls the speed of changes on the external interface. Care must be taken to program this register properly so that the speed of the external bus corresponds to the speed of the external peripheral and puts acceptable current load on the pins. COUNT0 and COUNT1 are used in quad chip select mode when different baud rates are selected, Section 16.5.8or Section 16.5.9. If different baud rates are used, COUNT0 is associated with the address range specified by CS2n and COUNT1 is associated with the address range specified by CS3n.
The COUNTn field is not a straight divider or count. The EPI Clock on EPI0S31 is related to the COUNTn field and the system clock as follows:
If COUNTn = 0,
otherwise:
where the symbol around COUNTn /2 is the floor operator, meaning the largest integer less than or equal to COUNTn /2.
So, for example, a COUNTn of 0x0001 results in a clock rate of 1/2(system clock); a COUNTn of 0x0002 or 0x0003 results in a clock rate of 1/4 (system clock).
EPIBAUD2 is shown in Figure 16-32 and described in Table 16-16.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
COUNT1 | COUNT0 | ||||||||||||||||||||||||||||||
R/W-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||