SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
EPI Configuration (EPICFG)
NOTE
The MODE field determines which configuration register is accessed for offsets 0x010 and 0x014. Any write to the EPICFG register resets the register contents at offsets 0x010 and 0x014.
The configuration register is used to enable the block, select a mode, and select the basic pin use (based on the mode). Note that attempting to program an undefined MODE field clears the BLKEN bit and disables the EPI controller.
EPICFG is shown in Figure 16-30 and described in Table 16-14.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | INTDIV | ||||||
R-0x0 | R/W-0x0 | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | BLKEN | MODE | |||||
R-0x0 | R/W-0x0 | R/W-0x0 | |||||