16.5.17 EPIFIFOLVL Register (Offset = 0x200) [reset = 0x33]
EPI FIFO Level Selects (EPIFIFOLVL)
This register allows selection of the FIFO levels which trigger an interrupt to the interrupt controller or, more efficiently, a DMA request to the µDMA. The NBRFIFO select triggers on fullness such that it triggers on match or above (more full) in order for the processor or the µDMA to extract the read data. The WFIFO triggers on emptiness such that it triggers on match or below (less entries) in order for the processor or the µDMA to insert more write data.
It should be noted that the FIFO triggers are not identical to other such FIFOs in other peripherals. In particular, empty and full triggers are provided to avoid wait states when using blocking operations.
The settings in this register are only meaningful if the µDMA is active or the interrupt is enabled.
Additionally, this register allows protection against writes stalling and notification of performing blocking reads which stall for extra time due to preceding writes. The two functions behave in a non-orthogonal way because read and write are not orthogonal.
The write error bit configures the system such that an attempted write to an already full WFIFO abandons the write and signals an error interrupt to prevent accidental latencies due to stalling writes.
The read error bit configures the system such that after a read has been stalled due to any preceding writes in the WFIFO, the error interrupt is generated. Note that the excess stall is not prevented, but an interrupt is generated after the fact to notify that it has happened.
EPIFIFOLVL is shown in Figure 16-46 and described in Table 16-30.
Return to Summary Table.
Figure 16-46 EPIFIFOLVL Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
WFERR |
RSERR |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
| R-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
WRFIFO |
RESERVED |
RDFIFO |
| R-0x0 |
R/W-0x3 |
R-0x0 |
R/W-0x3 |
|
Table 16-30 EPIFIFOLVL Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-18 |
RESERVED |
R |
0x0 |
|
| 17 |
WFERR |
R/W |
0x0 |
Write Full Error
0x0 = The Write Full error interrupt is disabled. Writes are stalled when the WFIFO is full until a space becomes available but an error is not generated. Note that the Cortex-M4 write buffer may hide that stall if no other memory transactions are attempted during that time.
0x1 = This bit enables the Write Full error interrupt (WTFULL in the EPIEISC register) to be generated when a write is attempted and the WFIFO is full. The write stalls until a WFIFO entry becomes available.
|
| 16 |
RSERR |
R/W |
0x0 |
Read Stall Error Note that the configuration of this bit has no effect on non-blocking reads.
0x0 = The Read Stalled error interrupt is disabled. Reads behave as normal and are stalled until any preceding writes have completed and the read has returned a result.
0x1 = This bit enables the Read Stalled error interrupt (RSTALL in the EPIEISC register) to be generated when a read is attempted and the WFIFO is not empty. The read is still stalled during the time the WFIFO drains, but this error notifies the application that this excess delay has occurred.
|
| 15-7 |
RESERVED |
R |
0x0 |
|
| 6-4 |
WRFIFO |
R/W |
0x3 |
Write FIFO
0x0 = reserved
0x1 = reserved
0x2 = Interrupt is triggered until there are only two slots available. Thus, trigger is deasserted when there are two WRFIFO entries present. This configuration is optimized for bursts of 2.
0x3 = Interrupt is triggered until there is one WRFIFO entry available. This configuration expects only single writes.
0x4 = Trigger interrupt when WRFIFO is not full, meaning trigger will continue to assert until there are four entries in the WRFIFO.
|
| 3 |
RESERVED |
R |
0x0 |
|
| 2-0 |
RDFIFO |
R/W |
0x3 |
Read FIFO This field configures the trigger point for the NBRFIFO.
0x0 = reserved
0x1 = Trigger when there are 1 or more entries in the NBRFIFO.
0x2 = Trigger when there are 2 or more entries in the NBRFIFO.
0x3 = Trigger when there are 4 or more entries in the NBRFIFO.
0x4 = Trigger when there are 6 or more entries in the NBRFIFO.
0x5 = Trigger when there are 7 or more entries in the NBRFIFO.
0x6 = Trigger when there are 8 entries in the NBRFIFO.
0x7 = reserved
|