| 31 |
CLKGATE |
R/W |
0x0 |
Clock Gated A software application should only set the CLKGATE bit when there are no pending transfers or no EPI register access has been issued.
0x0 = The EPI clock is free running.
0x1 = The EPI clock is held low.
|
| 30 |
CLKGATEI |
R/W |
0x0 |
Clock Gated Idle Note that EPI0S32 is an iRDY signal if RDYEN is set.
CLKGATEI is ignored if CLKPIN is 0 or if the COUNT0 field in the EPIBAUD register is cleared.
0x0 = The EPI clock is free running.
0x1 = The EPI clock is output only when there is data to write or read (current transaction); otherwise the EPI clock is held low.
|
| 29 |
CLKINV |
R/W |
0x0 |
Invert Output Clock Enable If operating in asynchronous mode, CLKINV must be 0.
0x0 = No effect.
0x1 = Invert EPI clock to ensure the rising edge is centered for outbound signal's setup and hold. Inbound signal is captured on rising edge EPI clock.
|
| 28 |
RDYEN |
R/W |
0x0 |
Input Ready Enable
0x0 = No effect.
0x1 = An external ready (iRDY) can be used to control the continuation of the current access. If this bit is set and the iRDY signal (EPIS032) is low, the current access is stalled.
|
| 27 |
IRDYINV |
R/W |
0x0 |
Input Ready Invert
0x0 = No effect.
0x1 = Invert polarity of incoming external ready. If this bit is set and the iRDY signal (EPIS032) is high the current access is stalled.
|
| 26-24 |
RESERVED |
R |
0x0 |
|
| 23 |
XFFEN |
R/W |
0x0 |
External FIFO FULL Enable
0x0 = No effect.
0x1 = An external FIFO full signal can be used to control write cycles. If this bit is set and the FFULL signal is high, XFIFO writes are stalled.
|
| 22 |
XFEEN |
R/W |
0x0 |
External FIFO EMPTY Enable
0x0 = No effect.
0x1 = An external FIFO empty signal can be used to control read cycles. If this bit is set and the FEMPTY signal is high, XFIFO reads are stalled.
|
| 21 |
WRHIGH |
R/W |
0x0 |
WRITE Strobe Polarity
0x0 = The WRITE strobe for CS0n is WRn (active Low).
0x1 = The WRITE strobe for CS0n is WR (active High).
|
| 20 |
RDHIGH |
R/W |
0x0 |
READ Strobe Polarity
0x0 = The READ strobe for CS0n is RDn (active Low).
0x1 = The READ strobe for CS0n is RD (active High).
|
| 19 |
ALEHIGH |
R/W |
0x1 |
ALE Strobe Polarity
0x0 = The address latch strobe for CS0n is ALEn (active Low).
0x1 = The address latch strobe for CS0n is ALE (active High).
|
| 18 |
WRCRE |
R/W |
0x0 |
PSRAM Configuration Register Write Used for PSRAM configuration registers.
With WRCRE set, the next transaction by the EPI will be a write of the CR bit field in the EPIHBPSRAM register to the configuration register (CR) of the PSRAM.
The WRCRE bit will self clear once the write-enabled CRE access is complete.
0x0 = No Action.
0x1 = Start CRE write transaction for CS0n.
|
| 17 |
RDCRE |
R/W |
0x0 |
PSRAM Configuration Register Read Enables read of PSRAM configuration registers.
With the RDCRE set, the next access is a read of the PSRAM's Configuration Register (CR).
This bit self clears once the read-enabled CRE access is complete.
The address for the CRE access is located at EPIHBPSRAM
[19:18].
The read data is returned on EPIHBPSRAM
[15:0].
0x0 = No Action.
0x1 = Start CRE read transaction for CS0n.
|
| 16 |
BURST |
R/W |
0x0 |
Burst Mode Burst mode must be used with an ALE-enabled interface.
Burst mode must be used with ADMUX, which is configured by the MODE field in the EPIHB16CFG register.
Burst mode is optimized for word-length accesses.
0x0 = Burst mode is disabled.
0x1 = Burst mode is enabled for CS0n or single chip access.
|
| 15-8 |
MAXWAIT |
R/W |
0xFF |
Maximum Wait This field defines the maximum number of external clocks to wait while an external FIFO ready signal is holding off a transaction (FFULL and FEMPTY).
When this field is clear, the transaction can be held off forever without a system interrupt.
When the MODE field is configured to be 0x3 and the BLKEN bit is set in the EPICFG register, enabling HB16 mode, this field defaults to 0xFF. |
| 7-6 |
WRWS |
R/W |
0x0 |
Write Wait States This field adds wait states to the data phase of CS0n (the address phase is not affected).
The effect is to delay the rising edge of WRn (or the falling edge of WR).
Each wait state adds 2 EPI clock cycles to the access time.
The WRWSM bit EPIHB16TIME register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
This field is not applicable in BURST mode.
This field is used in conjunction with the EPIBAUD register.
0x0 = Active WRn is 2 EPI clocks.
0x1 = Active WRn is 4 EPI clocks.
0x2 = Active WRn is 6 EPI clocks.
0x3 = Active WRn is 8 EPI clocks.
|
| 5-4 |
RDWS |
R/W |
0x0 |
Read Wait States This field adds wait states to the data phase of CS0n (the address phase is not affected).
The effect is to delay the rising edge of RDn/Oen (or the falling edge of RD).
Each wait state adds 2 EPI clock cycles to the access time.
The RDWSM bit in the EPIHB16TIME register can decrease the number of wait states by 1 EPI clock cycle for greater granularity.
This field is not applicable in BURST mode.
This field is used in conjunction with the EPIBAUD register
0x0 = Active RDn is 2 EPI clocks.
0x1 = Active RDn is 4 EPI clocks.
0x2 = Active RDn is 6 EPI clocks.
0x3 = Active RDn is 8 EPI clocks.
|
| 3 |
RESERVED |
R |
0x0 |
|
| 2 |
BSEL |
R/W |
0x0 |
Byte Select Configuration This bit enables byte select operation.
If BSEL = 0, byte accesses cannot be executed.
0x0 = No Byte SelectsData is read and written as 16 bits.
0x1 = Enable Byte SelectsTwo EPI signals function as byte select signals to allow 8-bit transfers. See for details on which EPI signals are used.
|
| 1-0 |
MODE |
R/W |
0x0 |
Host Bus Sub-Mode This field determines which of three Host Bus 16 sub-modes to use.
Submode use is determined by the connected external peripheral.
See for information on how this bit field affects the operation of the EPI signals.
When used with multiple chip select option and the CSBAUD bit is set to 1 in the EPIHB16CFG2 register, this configuration is for CS0n.
If the multiple chip select option is enabled and CSBAUD is clear, all chip-selects use the MODE encoding programmed in this register.
0x0 = ADMUX - AD[15:0]Data and Address are muxed.
0x1 = ADNONMUX - D[15:0]Data and address are separate. This mode is not practical in HB16 mode for normal peripherals because there are generally not enough address bits available.
0x2 = Continuous Read - D[15:0]This mode is the same as ADNONMUX, but uses address switch for multiple reads instead of OEn strobing. This mode is not practical in HB16 mode for normal SRAMs because there are generally not enough address bits available.
0x3 = XFIFO - D[15:0]This mode adds XFIFO controls with sense of XFIFO full and XFIFO empty. This mode uses no address or ALE.Note that the XFIFO can only be used in asynchronous mode.
|