SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
EPI Non-Blocking Read Data 0 (EPIRPSTD0), offset 0x028
EPI Non-Blocking Read Data 1 (EPIRPSTD1), offset 0x038
This register sets up a non-blocking read via the external interface. A non-blocking read is started by writing to this register with the count (other than 0). Clearing this register terminates an active non-blocking read as well as cancelling any that are pending. This register should always be cleared before writing a value other than 0; failure to do so can cause improper operation. Note that both NBR channels can be enabled at the same time, but NBR channel 0 has the highest priority and channel 1 does not start until channel 0 is finished.
The first address is based on the corresponding EPIRADDRn register. The address register is incremented by the size specified by the EPIRSIZEn register after each read. If the size is less than a word, only the least significant bits of data are filled into the NBRFIFO; the most significant bits are cleared.
Note that all three registers may be written using one STM instruction, such as with a structure copy in C/C++.
The data may be read from the EPIREADFIFO register after the read cycle is completed. The interrupt mechanism is normally used to trigger the FIFO reads via ISR or uDMA.
If the countdown has not reached 0 and the NBRFIFO is full, the external interface waits until a NBRFIFO entry becomes available to continue.
Note: if a blocking read or write is performed through the address mapped area (at 0x60000000 through 0xDFFFFFFF), any current non-blocking read is paused (at the next safe boundary), and the blocking request is inserted. After completion of any blocking reads or writes, the non-blocking reads continue from where they were paused.
The other way to read data is via the address mapped locations (see the EPIADDRMAP register), but this method is blocking (core or µDMA waits until result is returned).
To cancel a non-blocking read, clear this register. To make sure that all values read are drained from the NBRFIFO, the EPISTAT register must be consulted to be certain that bits NBRBUSY and ACTIVE are cleared. One of these registers should not be cleared until either the other EPIRPSTDn register becomes active or the external interface is not busy. At that point, the corresponding EPIRADDRn register indicates how many values were read.
EPIRPSTDn is shown in Figure 16-42 and described in Table 16-26.
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| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | POSTCNT | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||