SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The FPU sets the cumulative exception status flag in the FPSCR register as required for each instruction, in accordance with the FPv4 architecture. The FPU does not support user-mode traps. The exception enable bits in the FPSCR read-as-zero, and writes are ignored. The processor also has six output pins, FPIXC, FPUFC, FPOFC, FPDZC, FPIDC, and FPIOC, that each reflect the status of one of the cumulative exception flags. For a description of these outputs, see the Arm Cortex-M4 Integration and Implementation Manual.
The processor can reduce the exception latency by using lazy stacking. For more information, see Auxiliary Control Register (ACTLR). This means that the processor reserves space on the stack for the FP state, but does not save that state information to the stack. For more information, see the Armv7-M Architecture Reference Manual.