SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The GPIO Peripheral Configuration (GPIOPC) register controls the extended drive modes of the GPIO. When the EDE bit in GPIO Peripheral Properties (GPIOPP) register is set and the EDMn bit field for a GPIO pin is non-zero in the GPIOPC register, the GPIODRnR registers do not drive their default value, but instead output an incremental drive strength, which has an additive effect. This allows for more drive strength possibilities. When the EDE bit is set and the EDMn bit field is non-zero, the 2 mA driver is always enabled. Any bits enabled in the GPIODR4R register for a pin with a non-zero EDMn value, add an additional 2 mA. Any bits set in the GPIODR8R add an extra 4 mA of drive. The GPIODR12R register is only valid when the EDMn value is 0x3. For this encoding, setting a bit in the GPIODR12R register adds 4 mA of drive to the already existing 8 mA, for a 12 mA drive strength. To attain a 10-mA drive strength, the pin's GPIODR12R and GPIODR8R register should be enabled; this would result in the addition of two, 4-mA current drivers to the already enabled 2-mA driver. The table below shows the drive capability options. If EDMn is 0x00, then the GPIODR2R, GPIODR4R, and GPIODR8R function as stated in their default register description.
NOTE
A GPIOPC register write must precede the configuration of the GPIODRnR registers for extended drive mode to take effect.
| EDE (GPIOPP) | EDMn (GPIOPC) | GPIODR12R (+4 mA) | GPIODR8R (+4 mA) | GPIODR4R (+2 mA) | GPIODR2R (2 mA) | Drive (mA) |
|---|---|---|---|---|---|---|
| X | 0x0 | N/A | 0 | 0 | 1 | 2 |
| 0 | 1 | 0 | 4 | |||
| 1 | 0 | 0 | 8 | |||
| 1 | 0x1 | N/A | 0 | 0 | N/A | 2 |
| 0 | 1 | N/A | 4 | |||
| 1 | 0 | N/A | 6 | |||
| 1 | 1 | N/A | 8 | |||
| 1 | 0x3 | 0 | 0 | 0 | N/A | 2 |
| 0 | 0 | 1 | N/A | 4 | ||
| 0 | 1 | 0 | N/A | 6 | ||
| 0 | 1 | 1 | N/A | 8 | ||
| 1 | 1 | 0 | N/A | 10 | ||
| 1 | 1 | 1 | N/A | 12 | ||
| 1 | 0 | N/A | N/A | N/A | ||
| 1 | 0x2 | N/A | N/A | N/A | N/A | N/A |