SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Depending on the CPU frequency, the application must program the flash clock high time (FBCHT), flash bank clock edge (FBCE) and flash wait states (FWS) in the Memory Timing Parameter Register 0 for main flash and EEPROM (MEMTIM0) at System Control Module offset 0x0C0. Table 7-1 lists details the bit field values that are required for the given CPU frequency ranges.
| CPU Frequency Range (f) in MHz | Time Period Range (t) in ns | Flash Bank Clock High Time (FBCHT) | Flash Bank Clock Edge (FBCE) | Flash Wait States (FWS) |
|---|---|---|---|---|
| 16 | 62.5 | 0x0 | 1 | 0x0 |
| 16 < f ≤ 40 | 62.5 > t ≥ 25 | 0x2 | 0 | 0x1 |
| 40 < f ≤ 60 | 25 > t ≥ 16.67 | 0x3 | 0 | 0x2 |
| 60 < f ≤ 80 | 16.67 > t ≥ 12.5 | 0x4 | 0 | 0x3 |
| 80 < f ≤ 100 | 12.5 > t ≥ 10 | 0x5 | 0 | 0x4 |
| 100 < f ≤ 120 | 10 > t ≥ 8.33 | 0x6 | 0 | 0x5 |
To update the MEMTIM0 register with the new flash configuration values, the MEMTIMU bit must be set in the Run and Sleep Mode Configuration (RSCLKCFG) register at System Control offset 0x0B0.
NOTE
The associated flash and EEPROM fields in the MEMTIM0 register must be programmed to the same values. For example, the FWS field must be programmed to the same value as the EWS field.