SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The MSP432E4 devices provide a user-friendly interface for flash memory programming. All erase/program operations are handled by three registers: Flash Memory Address (FMA), Flash Memory Data (FMD), and Flash Memory Control (FMC). If the debug capabilities of the microcontroller have been deactivated, resulting in a locked state, a recovery sequence must be performed in order to reactivate the debug module (see Section 3.3.4.3).
When a flash memory operation write, page erase, or mass erase is executed in a flash bank, access to that particular bank pair is inhibited. As a result, instruction and literal fetches to the bank pair are held off until the flash memory operation is complete. If instruction execution is required during a flash memory operation, the code that is executing must be placed in SRAM and executed from there while the flash operation is in progress.
NOTE
When programming flash memory, the following characteristics of the memory must be considered: