SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Single and continuous transmission signal sequences for Freescale SPI format with SPO = 0 and SPH = 0 are shown in Figure 23-4 and Figure 23-5.
NOTE
This is the only Freescale SPI frame format configuration that can be used when operating in advanced, bi-, quad-SSI mode.
In this configuration, during idle periods:
If the QSSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSInFss master signal being driven low, causing slave data to be enabled onto the SSInDAT1 and SSInRX input line of the master. The master SSInDAT0 and SSInTX output pad is enabled.
One half SSInClk period later, valid master data is transferred to the SSInDAT0 and SSInTX pin. Once both the master and slave data have been set, the SSInClk master clock pin goes High after one additional half SSInClk period.
The data is now captured on the rising and propagated on the falling edges of the SSInClk signal.
In the case of a single word transmission, after all bits of the data word have been transferred, the SSInFss line is returned to its idle High state one SSInClk period after the last bit has been captured.
However, in the case of continuous back-to-back transmissions, the SSInFss signal must be pulsed High between each data word transfer because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the SPH bit is clear. Therefore, the master device must raise the SSInFss pin of the slave device between each data transfer to enable the serial peripheral data write. On completion of the continuous transfer, the SSInFss pin is returned to its idle state one SSInClk period after the last bit has been captured.