SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The transfer signal sequence for Freescale SPI format with SPO = 0 and SPH = 1 is shown in Figure 23-6, which covers both single and continuous transfers.
NOTE
This Freescale SPI frame format configuration is only available when operating in legacy SSI mode of operation.
In this configuration, during idle periods:
If the QSSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSInFss master signal being driven low. The master SSInDAT0 and SSInTX output is enabled. After an additional one-half SSInClk period, both master and slave valid data are enabled onto their respective transmission lines. At the same time, the SSInClk is enabled with a rising edge transition.
Data is then captured on the falling edges and propagated on the rising edges of the SSInClk signal.
In the case of a single word transfer, after all bits have been transferred, the SSInFss line is returned to its idle High state one SSInClk period after the last bit has been captured.
For continuous back-to-back transfers, the SSInFss pin is held Low between successive data words, and termination is the same as that of the single word transfer.