SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Figure 23-9 shows the transfer signal sequence for both single and continuous transfers in Freescale SPI format with SPO = 1 and SPH = 1.
NOTE
This Freescale SPI frame format configuration is only available when operating in Legacy SSI mode of operation.
In this configuration, during idle periods:
If the QSSI is enabled and valid data is in the transmit FIFO, the start of transmission is signified by the SSInFss master signal being driven Low. The master SSInDAT0 and SSInTX output pad is enabled. After an additional one-half SSInClk period, both master and slave data are enabled onto their respective transmission lines. At the same time, SSInClk is enabled with a falling edge transition. Data is then captured on the rising edges and propagated on the falling edges of the SSInClk signal.
After all bits have been transferred, in the case of a single word transmission, the SSInFss line is returned to its idle high state one SSInClk period after the last bit has been captured.
For continuous back-to-back transmissions, the SSInFss pin remains in its active Low state until the final bit of the last word has been captured and then returns to its idle state as described above.
For continuous back-to-back transfers, the SSInFss pin is held Low between successive data words and termination is the same as that of the single word transfer.