SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The µDMA controller is a flexible and highly configurable DMA controller designed to work efficiently with the Cortex-M4F processor core of the microcontroller. The µDMA controller supports multiple data sizes and address increment schemes, multiple levels of priority among DMA channels, and several transfer modes to allow for sophisticated programmed data transfers. Bus use by the µDMA controller is always subordinate to the processor core, so it never delays a bus transaction by the processor. Because the µDMA controller is only using otherwise idle bus cycles, the data transfer bandwidth it provides is essentially free, with no effect on the rest of the system. The bus architecture has been optimized to greatly enhance the ability of the processor core and the µDMA controller to efficiently share the on-chip bus, thus improving performance. The optimizations include RAM striping and peripheral bus segmentation, which in many cases let both the processor core and the µDMA controller access the bus and perform simultaneous data transfers.
Each peripheral function that is supported has a dedicated channel on the µDMA controller that can be configured independently. The µDMA controller implements a unique configuration method using channel control structures that are maintained in system memory by the processor. While simple transfer modes are supported, it is also possible to build up sophisticated "task" lists in memory that allow the µDMA controller to perform arbitrary-sized transfers to and from arbitrary locations as part of a single transfer request. The µDMA controller also supports the use of ping-pong buffering to accommodate constant streaming of data to or from a peripheral.
Each channel also has a configurable arbitration size. The arbitration size is the number of items that are transferred in a burst before the µDMA controller rearbitrates for channel priority. Using the arbitration size, it is possible to control exactly how many items are transferred to or from a peripheral each time the peripheral makes a µDMA service request.