SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
GPIO 8-mA Drive Select (GPIODR8R)
The GPIODR8R register is the 8-mA drive control register. Each GPIO signal in the port can be individually configured without affecting the other pads. When setting the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and DRV4 bit in the GPIODR4R register are automatically cleared by hardware. The 8-mA setting is also used for high-current operation.
NOTE
There is no configuration difference between 8-mA and high-current operation. The additional current capacity results from a shift in the VOH/ VOLlevels. See for further information.
NOTE
This register has no effect on port pins PL6 and PL7.
GPIODR8R is shown in Figure 17-17 and described in Table 17-20.
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31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DRV8 | ||||||||||||||||||||||||||||||
R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||