SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
GPIO Interrupt Sense (GPIOIS)
The GPIOIS register is the interrupt sense register. Setting a bit in the GPIOIS register configures the corresponding pin to detect levels, while clearing a bit configures the corresponding pin to detect edges. All bits are cleared by a reset.
NOTE
To prevent false interrupts, the following steps should be taken when re-configuring GPIO edge and interrupt sense registers:
GPIOIS is shown in Figure 17-7 and described in Table 17-9.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | IS | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||