SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
GPTM Clock Configuration (GPTMCC)
The GPTMCC register controls the clock source for the General-Purpose Timer module.
NOTE
When the ALTCLK bit is set in the GPTMCC register to enable using the alternate clock source, the synchronization imposes restrictions on the starting count value (down-count), terminal value (up-count) and the match value. This restriction applies to all modes of operation. Each event must be spaced by 4 Timer (ALTCLK) clock periods + 2 system clock periods. If some events do not meet this requirement, then it is possible that the timer block may need to be reset for correct functionality to be restored.
Example: ALTCLK= TPIOSC = 62.5 ns (16 MHz trimmed)
Thclk = 1 µs (1 MHz)
4 × 62.5 ns + 2 × 1 µs = 2.25 µs 2.25 µs / 62.5 ns = 36 (or 0x23)
The minimum values for the periodic or one-shot with a match interrupt enabled are: GPTMTAMATCHR = 0x23 GPTMTAILR = 0x46
GPTMCC is shown in Figure 18-36 and described in Table 18-39.
Return to Summary Table.
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
R-0x0 | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
R-0x0 | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
R-0x0 | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | ALTCLK | ||||||
R-0x0 | R/W-0x0 | ||||||