| 31-15 |
RESERVED |
R |
0x0 |
|
| 14 |
TBPWML |
R/W |
0x0 |
GPTM Timer B PWM Output Level
0x0 = Output is unaffected.
0x1 = Output is inverted.
|
| 13 |
TBOTE |
R/W |
0x0 |
GPTM Timer B Output Trigger Enable.
0x0 = The output Timer B ADC trigger is disabled.
0x1 = The output Timer B ADC trigger is enabled. In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register.
|
| 12 |
RESERVED |
R |
0x0 |
|
| 11-10 |
TBEVENT |
R/W |
0x0 |
GPTM Timer B Event Mode.
If PWM output inversion is enabled, edge detection interrupt behavior is reversed.
Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts.
Instead, the interrupt is generated on the negative edge of the PWM signal.
0x0 = Positive edge
0x1 = Negative edge
0x2 = Reserved
0x3 = Both edges
|
| 9 |
TBSTALL |
R/W |
0x0 |
GPTM Timer B Stall Enable.
If the processor is executing normally, the TBSTALL bit is ignored.
0x0 = Timer B continues counting while the processor is halted by the debugger.
0x1 = Timer B freezes counting while the processor is halted by the debugger.
|
| 8 |
TBEN |
R/W |
0x0 |
GPTM Timer B Enable
0x0 = Timer B is disabled.
0x1 = Timer B is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.
|
| 7 |
RESERVED |
R |
0x0 |
|
| 6 |
TAPWML |
R/W |
0x0 |
GPTM Timer A PWM Output Level.
0x0 = Output is unaffected.
0x1 = Output is inverted.
|
| 5 |
TAOTE |
R/W |
0x0 |
GPTM Timer A Output Trigger Enable.
In addition, the ADC must be enabled and the timer selected as a trigger source with the EMn bit in the ADCEMUX register (see ).
0x0 = The output Timer A ADC trigger is disabled.
0x1 = The output Timer A ADC trigger is enabled.
|
| 4 |
RTCEN |
R/W |
0x0 |
GPTM RTC Stall Enable If the RTCEN bit is set, it prevents the timer from stalling in all operating modes, even if TnSTALL is set.
0x0 = RTC counting freezes while the processor is halted by the debugger.
0x1 = RTC counting continues while the processor is halted by the debugger.
|
| 3-2 |
TAEVENT |
R/W |
0x0 |
GPTM Timer A Event Mode.
If PWM output inversion is enabled, edge detection interrupt behavior is reversed.
Thus, if a positive-edge interrupt trigger has been set and the PWM inversion generates a postive edge, no event-trigger interrupt asserts.
Instead, the interrupt is generated on the negative edge of the PWM signal.
0x0 = Positive edge
0x1 = Negative edge
0x2 = Reserved
0x3 = Both edges
|
| 1 |
TASTALL |
R/W |
0x0 |
GPTM Timer A Stall Enable.
If the processor is executing normally, the TASTALL bit is ignored.
0x0 = Timer A continues counting while the processor is halted by the debugger.
0x1 = Timer A freezes counting while the processor is halted by the debugger.
|
| 0 |
TAEN |
R/W |
0x0 |
GPTM Timer A Enable.
0x0 = Timer A is disabled.
0x1 = Timer A is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register.
|