| 31-14 |
RESERVED |
R |
X |
|
| 13 |
DMABMIS |
R |
0x0 |
GPTM Timer B DMA Done Masked Interrupt.
This bit is cleared by writing a 1 to the DMABINT bit in the GPTMICR register.
0x0 = A Timer B DMA done interrupt has not occurred or is masked.
0x1 = An unmasked Timer B DMA done interrupthas occurred.
|
| 12 |
RESERVED |
R |
0x0 |
|
| 11 |
TBMMIS |
R |
0x0 |
GPTM Timer B Match Masked Interrupt.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register.
0x0 = A Timer B Mode Match interrupt has not occurred or is masked.
0x1 = An unmasked Timer B Mode Match interrupthas occurred.
|
| 10 |
CBEMIS |
|
0x0 |
GPTM Timer B Capture Mode Event Masked Interrupt.
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register.
0x0 = A Capture B event interrupt has not occurred or is masked.
0x1 = An unmasked Capture B event interrupthas occurred.
|
| 9 |
CBMMIS |
R |
0x0 |
GPTM Timer B Capture Mode Match Masked Interrupt.
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register.
0x0 = A Capture B Mode Match interrupt has not occurred or is masked.
0x1 = An unmasked Capture B Match interrupthas occurred.
|
| 8 |
TBTOMIS |
R |
X |
GPTM Timer B Time-Out Masked Interrupt.
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register.
0x0 = A Timer B Time-Out interrupt has not occurred or is masked.
0x1 = An unmasked Timer B Time-Out interrupthas occurred.
|
| 7-6 |
RESERVED |
R |
0x0 |
|
| 5 |
DMAAMIS |
R |
0x0 |
GPTM Timer A DMA Done Masked Interrupt.
This bit is cleared by writing a 1 to the DMAAINT bit in the GPTMICR register.
0x0 = A Timer A DMA done interrupt has not occurred or is masked.
0x1 = An unmasked Timer A DMA done interrupthas occurred.
|
| 4 |
TAMMIS |
R |
0x0 |
GPTM Timer A Match Masked Interrupt This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register.
0x0 = A Timer A Mode Match interrupt has not occurred or is masked.
0x1 = An unmasked Timer A Mode Match interrupthas occurred.
|
| 3 |
RTCMIS |
R |
0x0 |
GPTM RTC Masked Interrupt.
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR register.
0x0 = An RTC event interrupt has not occurred or is masked.
0x1 = An unmasked RTC event interrupthas occurred.
|
| 2 |
CAEMIS |
R |
0x0 |
GPTM Timer A Capture Mode Event Masked Interrupt.
This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register.
0x0 = A Capture A event interrupt has not occurred or is masked.
0x1 = An unmasked Capture A event interrupthas occurred.
|
| 1 |
CAMMIS |
R |
0x0 |
GPTM Timer A Capture Mode Match Masked Interrupt.
This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register.
0x0 = A Capture A Mode Match interrupt has not occurred or is masked.
0x1 = An unmasked Capture A Match interrupthas occurred.
|
| 0 |
TATOMIS |
R |
0x0 |
GPTM Timer A Time-Out Masked Interrupt.
This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register.
0x0 = A Timer A Time-Out interrupt has not occurred or is masked.
0x1 = An unmasked Timer A Time-Out interrupthas occurred.
|