| 31-14 |
RESERVED |
R |
0x0 |
|
| 13 |
DMABRIS |
R |
0x0 |
GPTM Timer B DMA Done Raw Interrupt Status.
0x0 = The Timer B DMA transfer has not completed.
0x1 = The Timer B DMA transfer has completed.
|
| 12 |
RESERVED |
R |
0x0 |
|
| 11 |
TBMRIS |
R |
0x0 |
GPTM Timer B Match Raw Interrupt.
This bit is cleared by writing a 1 to the TBMCINT bit in the GPTMICR register.
0x0 = The match value has not been reached.
0x1 = The TBMIE bit is set in the GPTMTBMR register, and the match values in the GPTMTBMATCHR and (optionally) GPTMTBPMR registers have been reached when configured in one-shot or periodic mode.
|
| 10 |
CBERIS |
R |
0x0 |
GPTM Timer B Capture Mode Event Raw Interrupt.
This bit is cleared by writing a 1 to the CBECINT bit in the GPTMICR register.
0x0 = The capture mode event for Timer B has not occurred.
0x1 = A capture mode event has occurred for Timer B. This interrupt asserts when the subtimer is configured in Input Edge-Time mode.
|
| 9 |
CBMRIS |
R |
0x0 |
GPTM Timer B Capture Mode Match Raw Interrupt.
This bit is cleared by writing a 1 to the CBMCINT bit in the GPTMICR register.
0x0 = The capture mode match for Timer B has not occurred.
0x1 = The capture mode match has occurred for Timer B. This interrupt asserts when the values in the GPTMTBR and GPTMTBPR match the values in the GPTMTBMATCHR and GPTMTBPMR when configured in Input Edge-Time mode.
|
| 8 |
TBTORIS |
R |
0x0 |
GPTM Timer B Time-Out Raw Interrupt.
This bit is cleared by writing a 1 to the TBTOCINT bit in the GPTMICR register.
0x0 = Timer B has not timed out.
0x1 = Timer B has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches it's count limit (0 or the value loaded into GPTMTBILR, depending on the count direction).
|
| 7-6 |
RESERVED |
R |
0x0 |
|
| 5 |
DMAARIS |
R |
0x0 |
GPTM Timer A DMA Done Raw Interrupt Status.
0x0 = The Timer A DMA transfer has not completed.
0x1 = The Timer A DMA transfer has completed.
|
| 4 |
TAMRIS |
R |
0x0 |
GPTM Timer A Match Raw Interrupt.
This bit is cleared by writing a 1 to the TAMCINT bit in the GPTMICR register.
0x0 = The match value has not been reached.
0x1 = The TAMIE bit is set in the GPTMTAMR register, and the match value in the GPTMTAMATCHR and (optionally) GPTMTAPMR registers have been reached when configured in one-shot or periodic mode.
|
| 3 |
RTCRIS |
R |
0x0 |
GPTM RTC Raw Interrupt.
This bit is cleared by writing a 1 to the RTCCINT bit in the GPTMICR register.
0x0 = The RTC event has not occurred.
0x1 = The RTC event has occurred.
|
| 2 |
CAERIS |
R |
0x0 |
GPTM Timer A Capture Mode Event Raw Interrupt This bit is cleared by writing a 1 to the CAECINT bit in the GPTMICR register.
0x0 = The capture mode event for Timer A has not occurred.
0x1 = A capture mode event has occurred for Timer A. This interrupt asserts when the subtimer is configured in Input Edge-Time mode.
|
| 1 |
CAMRIS |
R |
0x0 |
GPTM Timer A Capture Mode Match Raw Interrupt.
This bit is cleared by writing a 1 to the CAMCINT bit in the GPTMICR register.
0x0 = The capture mode match for Timer A has not occurred.
0x1 = A capture mode match has occurred for Timer A. This interrupt asserts when the values in the GPTMTAR and GPTMTAPR match the values in the GPTMTAMATCHR and GPTMTAPMR when configured in Input Edge-Time mode.
|
| 0 |
TATORIS |
R |
0x0 |
GPTM Timer A Time-Out Raw Interrupt.
This bit is cleared by writing a 1 to the TATOCINT bit in the GPTMICR register.
0x0 = Timer A has not timed out.
0x1 = Timer A has timed out. This interrupt is asserted when a one-shot or periodic mode timer reaches it's count limit (0 or the value loaded into GPTMTAILR, depending on the count direction).
|