SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 6-2 lists the memory-mapped registers for the HIB. All register offset addresses not listed in Table 6-2 should be considered as RESERVED locations and the register contents should not be modified.
All addresses given are relative to the Hibernation Module base address at 0x400FC000 (ending address of 0x400FCFFF). The system clock to the Hibernation module must be enabled before the registers can be programmed (see Section 4.2.90). There must be a delay of 3 system clocks after the Hibernation module clock is enabled before any Hibernation module registers are accessed. In addition, the CLK32EN bit in the HIBCTL register must be set before accessing any other Hibernation module register.
NOTE
Except for the HIBIO and a portion of the HIBIC register, all other Hibernation module registers are on the Hibernation module clock domain and have special timing requirements. Software should make use of the WRC bit in the HIBCTL register to ensure that the required timing gap has elapsed. If the WRC bit is clear, any attempted write access is ignored (see Section 6.3.1). The HIBIO register and bits RSTWK, PADIOWK, and WC of the HIBIC register do not require waiting for write to complete. Because these registers are clocked by the system clock, writes to these registers and bits are immediate.
Writing to registers other than the HIBCTL and HIBIM before the CLK32EN bit in the HIBCTL register has been set may produce unexpected results.
NOTE
The Hibernation module registers are reset under two conditions:
Any other reset condition is ignored by the Hibernation module.
The following registers can be accessed only through privileged mode (see Section 4 for more details) :
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | HIBRTCC | Hibernation RTC Counter | Section 6.5.1 |
| 0x4 | HIBRTCM0 | Hibernation RTC Match 0 | Section 6.5.2 |
| 0xC | HIBRTCLD | Hibernation RTC Load | Section 6.5.3 |
| 0x10 | HIBCTL | Hibernation Control | Section 6.5.4 |
| 0x14 | HIBIM | Hibernation Interrupt Mask | Section 6.5.5 |
| 0x18 | HIBRIS | Hibernation Raw Interrupt Status | Section 6.5.6 |
| 0x1C | HIBMIS | Hibernation Masked Interrupt Status | Section 6.5.7 |
| 0x20 | HIBIC | Hibernation Interrupt Clear | Section 6.5.8 |
| 0x24 | HIBRTCT | Hibernation RTC Trim | Section 6.5.9 |
| 0x28 | HIBRTCSS | Hibernation RTC Sub Seconds | Section 6.5.10 |
| 0x2C | HIBIO | Hibernation IO Configuration | Section 6.5.11 |
| 0x30 to 0x6F | HIBDATA | Hibernation Data | Section 6.5.12 |
| 0x300 | HIBCALCTL | Hibernation Calendar Control | Section 6.5.13 |
| 0x310 | HIBCAL0 | Hibernation Calendar 0 | Section 6.5.14 |
| 0x314 | HIBCAL1 | Hibernation Calendar 1 | Section 6.5.15 |
| 0x320 | HIBCALLD0 | Hibernation Calendar Load 0 | Section 6.5.16 |
| 0x324 | HIBCALLD1 | Hibernation Calendar Load 1 | Section 6.5.17 |
| 0x330 | HIBCALM0 | Hibernation Calendar Match 0 | Section 6.5.18 |
| 0x334 | HIBCALM1 | Hibernation Calendar Match 1 | Section 6.5.19 |
| 0x360 | HIBLOCK | Hibernation Lock | Section 6.5.20 |
| 0x400 | HIBTPCTL | HIB Tamper Control | Section 6.5.21 |
| 0x404 | HIBTPSTAT | HIB Tamper Status | Section 6.5.22 |
| 0x410 | HIBTPIO | HIB Tamper I/O Control | Section 6.5.23 |
| 0x4E0 | HIBTPLOG0 | HIB Tamper Log 0 | Section 6.5.24 |
| 0x4E4 | HIBTPLOG1 | HIB Tamper Log 1 | Section 6.5.25 |
| 0x4E8 | HIBTPLOG2 | HIB Tamper Log 2 | Section 6.5.24 |
| 0x4EC | HIBTPLOG3 | HIB Tamper Log 3 | Section 6.5.25 |
| 0x4F0 | HIBTPLOG4 | HIB Tamper Log 4 | Section 6.5.24 |
| 0x4F4 | HIBTPLOG5 | HIB Tamper Log 5 | Section 6.5.25 |
| 0x4F8 | HIBTPLOG6 | HIB Tamper Log 6 | Section 6.5.24 |
| 0x4FC | HIBTPLOG7 | HIB Tamper Log 7 | Section 6.5.25 |
| 0xFC0 | HIBPP | Hibernation Peripheral Properties | Section 6.5.26 |
| 0xFC8 | HIBCC | Hibernation Clock Control | Section 6.5.27 |
Complex bit access types are encoded to fit into small table cells. Table 6-3 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| W1C | 1C
W |
1 to clear
Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |