SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
I2C Master Clock Low Time-out Count (I2CMCLKOCNT)
This register contains the upper 8 bits of a 12-bit counter that can be used to keep the timeout limit for clock stretching by a remote slave. The lower four bits of the counter are not user visible and are always 0x0.
NOTE
The Master Clock Low Time-out counter counts for the entire time SCL is held Low continuously. If SCL is deasserted at any point, the Master Clock Low Time-out Counter is reloaded with the value in the I2CMCLKOCNT register and begins counting down from this value.
I2CMCLKOCNT is shown in Figure 19-26 and described in Table 19-16.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | CNTL | ||||||||||||||||||||||||||||||
| R-0x0 | R/W-0x0 | ||||||||||||||||||||||||||||||