4.2.5 IMC Register (Offset = 0x54) [reset = 0x0]
Interrupt Mask Control (IMC)
This register contains the mask bits for system control raw interrupts. A raw interrupt, indicated by a bit being set in the Raw Interrupt Status (RIS) register, is sent to the interrupt controller if the corresponding bit in this register is set.
IMC is shown in Figure 4-11 and described in Table 4-15.
Return to Summary Table.
Figure 4-11 IMC Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
| RESERVED |
| R-0x0 |
|
| 23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
| RESERVED |
MOSCPUPIM |
| R-0x0 |
R/W-0x0 |
|
| 7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
PLLLIM |
RESERVED |
MOFIM |
RESERVED |
BORIM |
RESERVED |
| R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R-0x0 |
R/W-0x0 |
R-0x0 |
|
Table 4-15 IMC Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-9 |
RESERVED |
R |
0x0 |
|
| 8 |
MOSCPUPIM |
R/W |
0x0 |
MOSC Power Up Interrupt Mask
0x0 = The MOSCPUPRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the MOSCPUPRIS bit in the RIS register is set.
|
| 7 |
RESERVED |
R |
0x0 |
|
| 6 |
PLLLIM |
R/W |
0x0 |
PLL Lock Interrupt Mask
0x0 = The PLLLRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the PLLLRIS bit in the RIS register is set.
|
| 5-4 |
RESERVED |
R |
0x0 |
|
| 3 |
MOFIM |
R/W |
0x0 |
Main Oscillator Failure Interrupt Mask
0x0 = The MOFRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the MOFRIS bit in the RIS register is set.
|
| 2 |
RESERVED |
R |
0x0 |
|
| 1 |
BORIM |
R/W |
0x0 |
Brownout Reset Interrupt Mask
0x0 = The BORRIS interrupt is suppressed and not sent to the interrupt controller.
0x1 = An interrupt is sent to the interrupt controller when the BORRIS bit in the RIS register is set.
|
| 0 |
RESERVED |
R |
0x0 |
|