23.4 Initialization and Configuration
To enable and initialize the QSSI, the following steps are necessary:
- Enable the QSSI module using the RCGCSSI register (see Section 4.2.92).
- Enable the clock to the appropriate GPIO module through the RCGCGPIO register (see Section 4.2.87). To find out which GPIO port to enable, see the device-specific data sheet.
- Set the GPIO AFSEL bits for the appropriate pins (see Section 17.5.10). To determine which GPIOs to configure, see the device-specific data sheet.
- Configure the PMCn fields in the GPIOPCTL register to assign the QSSI signals to the appropriate pins. See Section 17.5.22 and the device-specific data sheet.
- Program the GPIODEN register to enable the pin's digital function. In addition, the drive strength, drain select and pullup and pulldown functions must be configured. See Section 17 for more information.
NOTE
Pullups can be used to avoid unnecessary toggles on the QSSI pins, which can take the slave to a wrong state. In addition, if the SSIClk signal is programmed to steady state high through the SPO bit in the SSICR0 register, then software must also configure the GPIO port pin corresponding to the SSInClk signal as a pullup in the GPIO Pullup Select (GPIOPUR) register.
For each of the frame formats, the QSSI is configured using the following steps:
- If initializing out of reset, ensure that the SSE bit in the SSICR1 register is clear before making any configuration changes. Otherwise, configuration changes for advanced SSI can be made while the SSE bit is set.
- Select whether the QSSI is a master or slave:
- For master operations, set the SSICR1 register to 0x0000.0000.
- For slave mode (output enabled), set the SSICR1 register to 0x0000.0004.
- For slave mode (output disabled), set the SSICR1 register to 0x0000.000C.
- Configure the QSSI clock source by writing to the SSICC register.
- Configure the clock prescale divisor by writing the SSICPSR register.
- Write the SSICR0 register with the following configuration:
- Serial clock rate (SCR)
- Desired clock phase and polarity, if using Freescale SPI mode (SPH and SPO)
- The protocol mode: Freescale SPI or TI SSF
- The data size (DSS)
- (Optional) Configure the SSI module for µDMA use with the following steps:
- Configure a µDMA for SSI use. See Section 8 for more information.
- Enable the TX FIFO or RX FIFO of the SSI module by setting the TXDMAE or RXDMAE bit in the SSIDMACTL register.
- Optionally, enable the µDMA completion interrupt by setting the DMATXIM or DMARXIM bit in the SSIIM register.
NOTE
For a TX DMA completion interrupt, software must disable the µDMA transmit enable to the SSI by clearing the TXDMAE bit in the QSSI DMA Control (SSIDMACTL) register and then setting the DMATXIC bit in the SSIICR register. This clears the DMA completion interrupt. When the µDMA is needed to transmit more data, the TXDMAE bit must be set (enabled) again.
- If this is the first initialization out of reset, enable the QSSI by setting the SSE bit in the SSICR1 register.
As an example, assume the QSSI must be configured to operate with the following parameters:
- Master operation
- Freescale SPI mode (SPO = 1, SPH = 1)
- 1-Mbps bit rate
- 8 data bits
Assuming the system clock is 20 MHz, the bit rate calculation would be:
Equation 65. SSInClk = SysClk / (CPSDVSR × (1 + SCR)) 1 × 106 = 20 × 106 / (CPSDVSR × (1 + SCR))
In this case, if CPSDVSR = 0x2, SCR must be 0x9.
The configuration sequence would be as follows:
- Ensure that the SSE bit in the SSICR1 register is clear.
- Write the SSICR1 register with a value of 0x0000.0000.
- Write the SSICPSR register with a value of 0x0000.0002.
- Write the SSICR0 register with a value of 0x0000.09C7.
- The QSSI is then enabled by setting the SSE bit in the SSICR1 register.