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18.3.3.4 Input Edge-Time Mode
NOTE
For rising-edge detection, the input signal must be high for at least two system clock periods following the rising edge. Similarly, for falling edge detection, the input signal must be low for at least two system clock periods following the falling edge. Based on this criteria, the maximum input frequency for edge detection is 1/4 of the system frequency.
In Edge-Time mode, the timer is configured as a 24-bit up- or down-counter including the optional prescaler with the upper timer value stored in the GPTMTnPR register and the lower bits in the GPTMTnILR register. In this mode, the timer is initialized to the value loaded in the GPTMTnILR and GPTMTnPR registers when counting down and 0x0 when counting up. The timer is capable of capturing three types of events: rising edge, falling edge, or both. The timer is placed into Edge-Time mode by setting the TnCMR bit in the GPTMTnMR register, and the type of event that the timer captures is determined by the TnEVENT fields of the GPTMCTL register. Table 18-7 lists the values that are loaded into the timer registers when the timer is enabled.
Table 18-7 Counter Values When the Timer is Enabled in Input Event-Count Mode
| Register | Count Down Mode | Count Up Mode |
|---|---|---|
| TnR | GPTMTnILR | 0x0 |
| TnV | GPTMTnILR | 0x0 |
When software writes the TnEN bit in the GPTMCTL register, the timer is enabled for event capture. When the selected input event is detected, the current timer counter value is captured in the GPTMTnR and GPTMTnPS register and is available to be read by the microcontroller. The GPTM then asserts the CnERIS bit in the GPTM Raw Interrupt Status (GPTMRIS) register, and holds it until it is cleared by writing the GPTM Interrupt Clear (GPTMICR) register. If the capture mode event interrupt is enabled in the GPTM Interrupt Mask (GPTMIMR) register, the GPTM also sets the CnEMIS bit in the GPTM Masked Interrupt Status (GPTMMIS) register. In this mode, the GPTMTnR and GPTMTnPS registers hold the time at which the selected input event occurred while the GPTMTnV register hold s the free-running timer value. These registers can be read to determine the time that elapsed between the interrupt assertion and the entry into the ISR.
In addition to generating interrupts, an ADC and/or a µDMA trigger can be generated. The ADC trigger is enabled by setting the TnOTE bit in GPTMCTL and the event that activates the ADC is configured in the GPTM ADC Event (GPTMADCEV) register. The µDMA trigger is enabled by configuring the appropriate µDMA channel as well as the type of trigger selected in the GPTM DMA Event (GPTMDMAEV) register (see Section 8.3.4).
After an event has been captured, the timer does not stop counting. It continues to count until the TnEN bit is cleared. When the timer reaches the time-out value, it is reloaded with 0x0 in up-count mode and the value from the GPTMTnILR and GPTMTnPR registers in down-count mode.
Figure 18-3 shows how input edge timing mode works. In the diagram, it is assumed that the start value of the timer is the default value of 0xFFFF, and the timer is configured to capture rising edge events.
Each time a rising edge event is detected, the current count value is loaded into the GPTMTnR and GPTMTnPS registers, and held there until another rising edge is detected (at which point the new count value is loaded into the GPTMTnR and GPTMTnPS registers).
Figure 18-3 16-Bit Input Edge-Time Mode Example NOTE
When operating in Edge-time mode, the counter uses a modulo 224 count if the prescaler is enabled, or 216if not. If there is a possibility the edge could take longer than the count, then another timer configured in periodic-timer mode can be implemented to ensure detection of the missed edge. The periodic timer should be configured in such a way that:
- The periodic timer cycles at the same rate as the edge-time timer
- The periodic timer interrupt has a higher interrupt priority than the edge-time time-out interrupt.
- If the periodic timer interrupt service routine is entered, software must check if an edge-time interrupt is pending and if it is, the value of the counter must be subtracted by 1 before being used to calculate the snapshot time of the event.