SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Interrupts can be generated from the MAC as a result of various events in the MAC and submodules. MAC interrupts are enabled or disabled in the Ethernet MAC Interrupt Mask (EMACIM) register, MAC offset 0x03C. Each interrupt event can be masked by setting the corresponding mask bit in the EMACIM register.
The interrupt register bits in the Ethernet MAC Raw Interrupt Status (EMACRIS) register only indicate the submodule from which the event is reported. The application must read the corresponding status registers to clear the interrupt.