26.1 Introduction
The MSP432E4 controller includes eight Universal Asynchronous Receiver/Transmitter (UART) with the following features:
- Programmable baud-rate generator allowing speeds up to 7.5 Mbps for regular speed (divide by 16) and 15 Mbps for high speed (divide by 8)
- Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
- Programmable FIFO length, including 1-byte deep operation providing conventional double-buffered interface
- FIFO trigger levels of ⅛, ¼, ½, ¾, and ⅞
- Standard asynchronous communication bits for start, stop, and parity
- Line-break generation and detection
- Fully programmable serial interface characteristics
- 5, 6, 7, or 8 data bits
- Even, odd, stick, or no parity bit generation and detection
- 1 or 2 stop bit generation
- IrDA serial-IR (SIR) encoder and decoder providing
- Programmable use of IrDA SIR or UART input/output
- Support of IrDA SIR encoder and decoder functions for data rates up to 115.2 kbps half-duplex
- Support of normal 3/16 and low-power (1.41 to 2.23 μs) bit durations
- Programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration
- Support for communication with ISO 7816 smart cards
- Modem functionality available on the following UARTs:
- UART0 (modem flow control and modem status)
- UART1 (modem flow control and modem status)
- UART2 (modem flow control)
- UART3 (modem flow control)
- UART4 (modem flow control)
- EIA-485 9-bit support
- Standard FIFO-level and End-of-Transmission (EOT) interrupts
- Efficient transfers using Micro Direct Memory Access Controller (µDMA)
- Separate channels for transmit and receive
- Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level
- Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level
- Global Alternate Clock (ALTCLK) resource or System Clock (SYSCLK) can be used to generate the baud clock.