SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
A watchdog timer can generate a nonmaskable interrupt (NMI), a regular interrupt, or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or the failure of an external device to respond in the expected way. The MSP432E4 microcontroller has two Watchdog Timer Modules, one module is clocked by the system clock (Watchdog Timer 0) and the other module (Watchdog Timer 1) is clocked by the clock source programmed in the ALTCLK field of the Alternate Clock Configuration (ALTCLKCFG) register, System Control offset 0x138. The two modules are identical except that WDT1 is in a different clock domain, and therefore requires synchronizers. As a result, WDT1 has a bit defined in the Watchdog Timer Control (WDTCTL) register to indicate when a write to a WDT1 register is complete. Software can use this bit to ensure that the previous access has completed before starting the next access.
The MSP432E4 controller has two Watchdog Timer modules with the following features:
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. When the Watchdog Timer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered.