SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
Table 20-6 lists the memory-mapped registers for the LCD. All register offset addresses not listed in Table 20-6 should be considered as reserved locations and the register contents should not be modified.
The offsets are relative to the LCD module base address of 0x44050000.
| Offset | Acronym | Register Name | Section |
|---|---|---|---|
| 0x0 | LCDPID | LCD PID Register Format | Section 20.7.1 |
| 0x4 | LCDCTL | LCD Control | Section 20.7.2 |
| 0xC | LCDLIDDCTL | LCD LIDD Control | Section 20.7.3 |
| 0x10 | LIDDCS0CFG | LCD LIDD CS0 Configuration | Section 20.7.4 |
| 0x14 | LIDDCS0ADDR | LIDD CS0 Read/Write Address | Section 20.7.5 |
| 0x18 | LIDDCS0DATA | LIDD CS0 Data Read/Write Initiation | Section 20.7.6 |
| 0x1C | LIDDCS1CFG | LIDD CS1 Configuration | Section 20.7.7 |
| 0x20 | LIDDCS1ADDR | LIDD CS1 Address Read/Write Initiation | Section 20.7.8 |
| 0x24 | LIDDCS1DATA | LIDD CS1 Data Read/Write Initiation | Section 20.7.9 |
| 0x28 | LCDRASTRCTL | LCD Raster Control | Section 20.7.10 |
| 0x2C | LCDRASTRTIM0 | LCD Raster Timing 0 | Section 20.7.11 |
| 0x30 | LCDRASTRTIM1 | LCD Raster Timing 1 | Section 20.7.12 |
| 0x34 | LCDRASTRTIM2 | LCD Raster Timing 2 | Section 20.7.13 |
| 0x38 | LCDRASTRSUBP1 | LCD Raster Subpanel Display 1 | Section 20.7.14 |
| 0x3C | LCDRASTRSUBP2 | LCD Raster Subpanel Display 2 | Section 20.7.15 |
| 0x40 | LCDDMACTL | LCD DMA Control | Section 20.7.16 |
| 0x44 | LCDDMABAFB0 | LCD DMA Frame Buffer 0 Base Address | Section 20.7.17 |
| 0x48 | LCDDMACAFB0 | LCD DMA Frame Buffer 0 Ceiling Address | Section 20.7.18 |
| 0x4C | LCDDMABAFB1 | LCD DMA Frame Buffer 1 Base Address | Section 20.7.19 |
| 0x50 | LCDDMACAFB1 | LCD DMA Frame Buffer 1 Ceiling Address | Section 20.7.20 |
| 0x54 | LCDSYSCFG | LCD System Configuration Register | Section 20.7.21 |
| 0x58 | LCDRISSET | LCD Interrupt Raw Status and Set Register | Section 20.7.22 |
| 0x5C | LCDMISCLR | LCD Interrupt Status and Clear | Section 20.7.23 |
| 0x60 | LCDIM | LCD Interrupt Mask | Section 20.7.24 |
| 0x64 | LCDIENC | LCD Interrupt Enable Clear | Section 20.7.25 |
| 0x6C | LCDCLKEN | LCD Clock Enable | Section 20.7.26 |
| 0x70 | LCDCLKRESET | LCD Clock Resets | Section 20.7.27 |
Complex bit access types are encoded to fit into small table cells. Table 20-7 shows the codes that are used for access types in this section.
| Access Type | Code | Description |
|---|---|---|
| Read Type | ||
| R | R | Read |
| Write Type | ||
| W | W | Write |
| Reset or Default Value | ||
| -n | Value after reset or the default value | |