SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
MPU Region Attribute and Size (MPUATTR), offset 0xDA0
MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8
MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0
MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8
NOTE
This register can only be accessed from privileged mode.
The MPUATTR register defines the region size and memory attributes of the MPU region specified by the MPU Region Number (MPUNUMBER) register and enables that region and any subregions.
The MPUATTR register is accessible using word or halfword accesses with the most-significant halfword holding the region attributes and the least-significant halfword holds the region size and the region and subregion enable bits.
The MPU access permission attribute bits, XN, AP, TEX, S, C, and B, control access to the corresponding memory region. If an access is made to an area of memory without the required permissions, then the MPU generates a permission fault.
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register as follows:
(Region size in bytes) = 2(SIZE+1)
The smallest permitted region size is 32 bytes, corresponding to a SIZE value of 4. Table 2-47 gives example SIZE values with the corresponding region size and value of N in the MPU Region Base Address (MPUBASE) register.
| SIZE Encoding | Region Size | Value of N(1) | Note |
|---|---|---|---|
| 00100b (0x4) | 32 B | 5 | Minimum permitted size |
| 01001b (0x9) | 1 KB | 10 | - |
| 10011b (0x13) | 1 MB | 20 | - |
| 11101b (0x1D) | 1 GB | 30 | - |
| 11111b (0x1F) | 4 GB | No valid ADDR field in MPUBASE; the region occupies the complete memory map. | Maximum possible size |
MPUATTRn is shown in Figure 2-32 and described in Table 2-48.
Return to Summary Table.
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED | XN | RESERVED | AP | ||||
| R-0x0 | R/W-0x0 | R-0x0 | R/W-0x0 | ||||
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | TEX | S | C | B | |||
| R-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | R/W-0x0 | |||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| SRD | |||||||
| R/W-0x0 | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | SIZE | ENABLE | |||||
| R-0x0 | R/W-0x0 | R/W-0x0 | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31-29 | RESERVED | R | 0x0 | |
| 28 | XN | R/W | 0x0 |
Instruction Access Disable |
| 27 | RESERVED | R | 0x0 | |
| 26-24 | AP | R/W | 0x0 |
Access Privilege
|
| 23-22 | RESERVED | R | 0x0 | |
| 21-19 | TEX | R/W | 0x0 |
Type Extension Mask
|
| 18 | S | R/W | 0x0 |
Shareable
|
| 17 | C | R/W | 0x0 |
Cacheable
|
| 16 | B | R/W | 0x0 |
Bufferable
|
| 15-8 | SRD | R/W | 0x0 | Subregion Disable Bits
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, configure the SRD field as 0x00. See for more information. |
| 7-6 | RESERVED | R | 0x0 | |
| 5-1 | SIZE | R/W | 0x0 | Region Size Mask
The SIZE field defines the size of the MPU memory region specified by the MPUNUMBER register. Refer to Table 2-47 for more information. |
| 0 | ENABLE | R/W | 0x0 |
Region Enable |