SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
The transfer of multiple packets is normally carried out using DMA Mode 1. Where multiple packets are to be received using DMA Mode 1, the DMA Controller should be programmed as follows:
The USB Rx endpoint should be programmed as follows:
As each packet is received by the USB, the DMA controller requests bus mastership and transfers the packet to memory. With AutoClear set, the USB automatically clears the RXRDY bit. In device mode or where Request Packet Count (COUNT) is zero, this process continues automatically until the USB receives a short packet (one of less than the maximum packet size for the endpoint) signifying the end of the transfer. This short packet is not be transferred by the DMA controller; instead, the USB interrupts the processor by generating the appropriate Endpoint interrupt. The processor can then read the USB Receive Byte Count Endpoint n (USBRXCOUNTn) register to see the size of the short packet and either unload it manually or reprogram the DMA controller in Mode 0 to unload the packet. In host mode with AUTORQ set and the USBRQPKTCOUNTn register non-zero, the USB decrements the value in the USBRQPKTCOUNTn register following each request. When the value decrements from 1 to 0, the AUTORQ bit is cleared to prevent any further transactions being attempted.
The USB DMA Address n (USBDMAADDRn) register is incremented as the packets were unloaded so the processor can determine the size of the transfer by comparing the current value of th USB DMA Address n (USBDMAADDRn) register against the start address of the memory buffer.
NOTE
If the size of the transfer exceeds the data buffer size, the DMA controller stops unloading the FIFO and interrupts the processor through a DMA interrupt.