22.5.9 ONEWIREDMA Register (Offset = 0x120) [reset = 0x0]
1-Wire uDMA Control (ONEWIREDMA), offset 0x120
The 1-Wire DMA Control (ONEWIREDMA) register is used to configure the uDMA operation for 1-Wire. This mechanism supports both uDMA write operations, uDMA read operations, small write/read operations, and scatter-gather support of mixed operations.
NOTE
This register is cleared when the dma_done signal to the 1-Wire module is asserted by the uDMA and the DMA bit in the ONEWIRERIS register is set.
ONEWIREDMA is shown in Figure 22-15 and described in Table 22-13.
Return to Summary Table.
Figure 22-15 ONEWIREDMA Register
| 31 |
30 |
29 |
28 |
27 |
26 |
25 |
24 |
23 |
22 |
21 |
20 |
19 |
18 |
17 |
16 |
| RESERVED |
| R-0x0 |
|
| 15 |
14 |
13 |
12 |
11 |
10 |
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
| RESERVED |
SG |
DMAOP |
RST |
| R-0x0 |
R/W-0x0 |
R/W-0x0 |
R/W-0x0 |
|
Table 22-13 ONEWIREDMA Register Field Descriptions
| Bit |
Field |
Type |
Reset |
Description |
| 31-4 |
RESERVED |
R |
0x0 |
|
| 3 |
SG |
R/W |
0x0 |
Scatter-Gather Enable. This bit should be enabled when DMAOP = 0x1 and the scatter-gather method is being used. This bit self clears after it has performed the µDMA request.
0x0 = No effect
0x1 = µDMA is requested at start of operation and all requests after are on completion of transactions.
|
| 2-1 |
DMAOP |
R/W |
0x0 |
µDMA Operation. The programmed operation starts when reset completes if the RST bit in the ONEWIRECS register is set. If RST is not set, then write requests the µDMA immediately and read starts on a write to the ONEWIREDATW register.
0x0 = µDMA disabled
0x1 = µDMA single read: 1-Wire requests µDMA to read ONEWIREDATR register after each read transaction.
0x2 = µDMA multiple write: 1-Wire requests µDMA to load whenever the ONEWIREDATW register is empty.
0x3 = µDMA multiple read: An initial read occurs and subsequent reads start after µDMA has read the ONEWIREDATR register.
|
| 0 |
RST |
R/W |
0x0 |
µDMA Reset.
0x0 = No effect.
0x1 = A reset is issued and no reads and writes should be started until reset is done. Setting this bit sets the RST bit in the ONEWIRECS register. This bit is self-clearing upon reset completion.
|