SLAU723A October 2017 – October 2018 MSP432E401Y , MSP432E411Y
When in device mode, OUT transactions are handled through the USB controller receive FIFOs. The sizes of the receive FIFOs for the seven configurable OUT endpoints are determined by the USB Receive FIFO Start Address (USBRXFIFOADD) register. The maximum amount of data received by an endpoint in any packet is determined by the value written to the USB Maximum Receive Data Endpoint n (USBRXMAXPn) register for that endpoint. When double-packet buffering is enabled, two data packets can be buffered in the FIFO. When double-packet buffering is disabled, only one packet can be buffered even if the packet is less than half the FIFO size.
NOTE
In all cases, the maximum packet size must not exceed the FIFO size.